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This paper presents a very low power and area efficient ASIC implementation of Advanced Encryption Standard Algorithm (AES). The implementation results of S-Box, MixColumn Transformation and overall AES encryption/ decryption are given in this paper. The AES has been implemented in 90nm standard CMOS library using Synopsys Design Compiler with a core voltage of 1.2V. The power dissipation of S-Box...
The objective of image fusion is to combine relevant information from two or more images of the same scene into a single composite image which is more informative and is more suitable for human and machine perception. In recent past, different methods of image fusion have been proposed in literature both in spatial domain and wavelet domain. Spatial domain based methods produce spatial distortions...
Anti Torpedo Defense System (ATDS) is a very vast system with infinite geometrics and corresponding Tactical Solutions. Also, a few geometries do exist, where the Tactical Solution can never be arrived optimally. The Purpose of the system is to analyze the generated Tactical Solution which enhance the ships survivability against enemy Torpedo using the Optimal decoy deployment logic and maximizing...
The advent of the internet age has led to the increase of prominent network security issues. Information encryption has long been a method used for information security. With the rapid development of parallel computing capacities of computer hardware, this method alone could not be trusted to ensure security by increasing the key sizes, thus bringing in the information hiding techniques into the scenario...
Impulse noise is a spark that affects the contents of digital images. It also occurs during image acquisition, transmission due to malfunctioning of pixel elements in the camera sensors, faulty memory locations, timing errors in analog to digital conversion and bit errors during transmission. Removal of impulse noise involves detection followed by filtering mechanism. There are two types of impulse...
To represent very large or small values, large range is required as the integer representation is no longer appropriate. These values can be represented using the IEEE-754 standard based floating point representation. This paper presents high speed ASIC implementation of a floating point arithmetic unit which can perform addition, subtraction, multiplication, division functions on 32-bit operands...
In this paper, we study the effect of using digitally controlled impedance IO Standard in memory interface design in terms of power consumption. In this work, we achieved 50% dynamic power reduction at 1.5V output driver voltage, 35.2% dynamic power reduction at 1.8V output driver voltage in comparison to 2.5V output driver voltage in DCI based IO standard implementation on input or output port in...
Due to the dynamic nature of the web plenty of webpages are deleted and added newly and as the web is large collection of data in form of the webpages or in the group of webpages as websites. So every time a surfer searches the web using the search engine, the data should be fresh and relevant. Due to the large size of web, corresponding to any query made by the user number of pages are being retrieved...
H.264, which is the most advanced video compression standard till date, includes novel algorithms for quantization and inverse quantization processes. In this paper, a new hardware architecture exclusively based on combinational logic is proposed for the quantizer and inverse quantizer blocks for real-time video processing. Implemented in Xilinx14.1, Virtex-5 technology, the proposed architectures...
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