The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A low-noise transconductance amplifier (LNTA) aimed at continuous-time ΣΔ wideband frontend is presented. In this application, the LNTA operates with a capacitive load to provide high linearity and sufficient Gm gain over a wide frequency band. By combination of various circuit techniques the LNTA, which is designed in 65nm CMOS, achieves in simulation the noise figure less than 1.35 dB and linearity...
This paper presents a pulse-width and position modulator (PWPM) topology suitable for digital centric polar transmitter frontends suitable for software defined radios. PWPM enables the usage of highly efficient switching-mode power amplifiers (SMPA) and direct control of the output power. The presented first implementation of the modulator targets 3GPP and Long Term Evolution (LTE) base-stations and...
The paper proposes effective solutions to include nonlinear inductors with soft ferromagnetic core in the time-domain circuit analyses. Three inductor models are developed, tested and compared. They are conceived for different degrees of accuracy related to the real devices. The models are robust and reliable due to the modeling concept that avoids numerical instabilities. An enhanced inductor model...
This paper presents a novel approach to design a programmable-bandwidth amplifier intended for ultra-low-power switched-capacitor application. The proposed topology is based on the common load-compensated two-stage OTA. The GBW is enhanced by replicating the second amplifying stage. Implemented in a 65-nm CMOS technology and approved by the post-layout simulation, the GBW is programmed in three operation...
In this paper, we provide a novel approach to describe and analyze memristive circuits. This method is based on a Volterra series representation of the essential time functions of the circuit. This does not only provide the possibility of calculating voltages and currents over time in specific memristive networks, but describes the behavior of a general single memristor circuit, e.g. a circuit with...
In this work, we recall the generalized exponential function in the fractional-order domain which enables defining generalized cosine and sine functions. We then re-visit some important trigonometric identities and generalize them from the narrow integer-order subset to the more general fractional-order domain. Generalized hyperbolic function relations are also given.
The aim of this paper is to describe a method of filter bank realization using the switched capacitor (SC) technique. The analysis of steps needed for this realization is performed. The correct solution requires the IIR filter bank synthesis followed by the conversion to SC circuits. Due to simplicity only the two-channel filter bank is used. The main points of the whole design procedure and key recommendations...
A discrete transmission line model is presented for propagation of quantum particles in crystals. It allows a substantial simplification in calculations, the integration of a quantum description in a classical environment, let alone a useful key for intuitive grasping of quantum aspects.
In this paper we present a novel topology of a class-AB flipped voltage follower (FVF) output stage. This stage has better slew-rate performance than the standard FVF buffer, and better linearity and output resistance than the standard class-AB stage. Besides, it achieves higher output voltage swing than other class-AB FVF buffers previously presented in the literature. It is thus suitable for low-voltage...
In order to support higher data rates of up to 5.76 Mbps in the uplink the UMTS specification is enhanced by HSUPA. These higher data rates are achieved by multiplexing more code channels on the same transmit bandwidth. For certain configurations the adjacent channel leakage is however also increased due to the power amplifier nonlinearities. Thus the standard requires a power back-off for these cases...
The reduction of the oxide thickness in advanced CMOS processes is one of the many advantages of technology downscaling, as it favors the reduction of the threshold voltage shifts due to radiation-induced gate oxide trapped charge. This inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. In this paper we present...
Testing the analog functions of a system-on-chip makes up the major portion of test cost - up to 50% according to anecdotal evidence - although analog circuits occupy less than 5% of the die area. Furthermore, cases have been reported where the test cost actually surpasses the overall manufacturing cost. This shows that analog test is in the coming years an area for industry focus, innovation and...
Very low frequency Gm-C filters are critical cells that should be carefully designed in order to avoid an excessive occupation of silicon area, especially when a high dynamic range is required. In this work we propose a routine, which exploits the MATLAB Optimization Toolbox in order to perform an optimum sizing of low frequency Gm-C integrators. The target is minimizing the integrator area, while...
In the paper, an efficient and reliable algorithm for solving the circuit algebraic-differential equations is characterized first, which is based on a sophisticated arrangement of the Newton interpolation polynomial. For enhancing the efficiency of repeated solutions of linear systems necessary in the Newton-Raphson method, a novel modification of the Markowitz criterion is suggested, which is compatible...
Computationally intensive problems can be represented with data-flow graphs and automatically transformed to locally controlled floating-point units via partitioning. In theory the lack of global control signals enables high performance implementation however placing and routing of the partitioned circuits are not trivial. In practice to create a high performance implementation the clusters should...
A method to analyze the injection locking and injection pulling of arbitrary oscillators under small excitation is proposed. The most general case when the excitation frequency is close to a rational fraction of the oscillator fundamental is considered. The phase differential equation for an arbitrary periodic excitation is derived. Expressions to evaluate characteristics of the oscillator in injection...
The effect of nonlinearities in injection-locked frequency dividers is investigated and it is shown that the presence of nonlinearities, such as in a CML DFF-based divider, results in a wider frequency locking range. A new divider topology is presented that exhibits both higher operating frequencies and similar wide-locking range compared to the conventional CML DFF-based topology. The chip was fabricated...
This paper describes an experimental technique for rapidly finding the boundaries of Arnold tongues. The method is suitable for characterizing the locking regions of injection-locked frequency dividers. The algorithm is described and examples are presented to demonstrate the value of the technique in comparing divider architectures with tail and direct injection.
We report an experimental technique for estimating the dispersion coefficient α of a constant phase element (CPE). The method employs using a setup to excite the impedance under consideration via a periodic triangle-wave current I(t). Measuring the 50% rise time of the developed voltage V (t) then enables finding α using a pre-calculated Table. Experimental results are shown.
In this paper, symbolic matrices and a simple algebraic method to list spanning trees and find Hamiltonian circuits in a simple un-oriented graph are used. A concrete, fully-parallel algorithm that achieves both goals, with examples is shown. A necessary and sufficient condition for Hamiltonicity is presented, too.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.