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High performance implementations of unary functions are important in many applications e.g. in the wireless communication area. This paper shows the development and VLSI implementation of unary functions like the logarithmic and exponential function, by using a novel approximation methodology based on parabolic synthesis, which is compared to the well known CORDIC algorithm. Both designs are synthesized...
Today's multi-media electronic era is driven by the increasing demand for small multifunctional devices able to support diverse services. Unfortunately, the high levels of transistor integration and performance required by such devices lead to an unprecedented increase of on-chip power that significantly limits the battery lifetime and even poses reliability concerns. Several techniques have been...
Computing Euclidean Distances is a very important operation in digital communication, especially in the case of trellis coded modulation, where it is used numerously. This paper shows that a substantial reduction in complexity can be achieved in hardware processing elements for computing Euclidean Distances. A reduction in complexity down to 39% is shown compared to traditional designs. The paper...
This paper shows a novel methodology to reduce the power consumption and complexity in unrolled CORDIC architectures. It is a methodology based on removing adder and subtractor stages starting from the first stage. The stages are replaced with a number of MUXes. Three to four stages can be removed with substantial reduction in complexity and power consumption. The methodology is applicable on CORDICs...
In this paper, modified, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and power consumption. Two different architectures are investigated, both have variable configurations of the input and output word-length (i.e., the physical resolution of the DAC). A modified architecture, termed in this work...
A new cyclic ADC structure achieving capacitor mismatch insensitivity is presented. This technique enables cyclic ADC to obtain a very precise residue voltage in cycles independent of matching of capacitors. In addition, this new structure saves the die area of capacitors in the switched capacitor network by 25% and significantly reduces power consumption by up to 40%. A 12-bit 1.67MS/s cyclic ADC...
The use of rate-compatible error correcting codes offers several advantages as compared to the use of fixed-rate codes: a smooth adaptation to the channel conditions, the possibility of incremental Hybrid ARQ schemes, as well as simplified code representations in the encoder and decoder. In this paper, the implementation of a decoder for rate-compatible quasi-cyclic LDPC codes is considered. The decoder...
This paper applies recently developed techniques for the PieceWise-Affine (PWA) approximation of explicit Model Predictive Control (MPC) to an Adaptive Cruise Control system. The optimal MPC law is approximated by using a particular class of PWA functions defined over a domain partitioned into simplices, referred to as PieceWise-Affine Simplicial functions. This approximation technique allows a very...
Galois field arithmetic circuits find wide variety of application in cryptography. Thus they faces majority of the hardware based attacks for malicious gain. Though there are many approaches that have been proposed to mitigate such malicious attacks, most of them are inappropriate for practical applicability due to various design drawbacks. It is noted that Galois field multipliers are one among the...
The paper discusses the possibility of using the dynamics of a class of Cellular Neural Networks (CNN's) for electrocardiogram (ECG) signals classification. The main idea is that of segmentation and transformation of the temporal signal into a 1D spatial one which is further processed by means of a bank of linear spatial filters using a parallel architecture of CNN type. A major advantage of the proposed...
This paper proposes high performance dedicated hardware architecture for the Haar Wavelet transform, whose structure is based on nine levels of decomposition. The architecture is described in hardware description language VHDL, and it has been designed by using fixed point arithmetic, and also using efficient arithmetic operators into their sub modules. The efficiency of the architecture was proved...
The size and performance of a system LSI depend heavily on the architecture which is chosen. As a result, the architecture design phase is one of the most important steps in the system LSI development process and is critical to the commercial success of a device. In this paper, we propose a C-based system LSI design methodology and apply it to the design of of a software and hardware system based...
Human's retina has the capability to identify color and luminosity. The cell identifies color is called a cone cell and identifies luminosity is called a rod cell. The color image processing using CNN was proposed by Roska et al. Additionally, Inoue et al. have used three-layer CNN based on cone cell, and performed edge enhancement. They have confirmed that edge had been detected under three-layer...
This paper employs a CMOS 0.18 µm CMOS technology to design a 6-bit 250 MS/s pipelined ADC with open-loop amplifiers. The amplifiers utilize MOS transistors in triode region instead of resistors and current sources to decrease the process variation and the need of bias circuits. The amplification managed with the global-gain-control loop which realizes the error amplifier with a comparator in low-bandwidth...
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