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This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed...
A fast integrated gate driver with amorphous silicon thin film transistor (a-Si:H TFT) is proposed in this paper. To improve the circuit speed, a new input scheme is designed to provide a full scale pre-charge voltage. So the loss of pre-charge voltage, a challenge in the conventional designs, is avoided. Simulations show that the proposed gate driver has a much improved driving speed in comparison...
A highly integrated 0.13um CMOS direct conversion transmitter front-end for wide-band code division multiple access (WCDMA) is presented. The transmitter delivers +6.8dBm output power while consuming 39mA. The overall gain can be programmed in 6dB steps over a 66dB range with 0.1dB accuracy. The transmitter front-end achieves an OIP3 with +19.2dBm, an error vector magnitude of 3.7%, and an adjacent...
In this paper a current mode logic (CML) transceiver with ±250mV output swing is proposed. The CML transceiver is designed according to inter-die communication model analysis. The model includes both bonding wire and transmission line based on electromagnetic analysis. The CML transceiver is implemented in 1.8V 0.18μm technology. Simulation results show that the transceiver can reach 2.4Gbps data...
The paper describes the design and implementation of a speaker driver applied to Class G/Class I with single phase power supply. Gain expanding and compressing technology are employed in signal processing circuit to optimize power dissipation. Experimental results using 0.18μm N-well CMOS show that it can obtain less than 0.006% THD at low power range and less than 0.4% at medium power range with...
A white LED driver chip applied in backlight is proposed, which is based on pulse width modulator. The design of modules such as current reference, oscillator and dynamic slope compensation are discussed in detail. The simulation results, based on CSMC 0.5μm BCD technology, show that the input voltage is in the range of 3.3~5.5V, the output voltage is up to 20V when the output current is between 15...
A variable gain and output power CMOS power amplifier is presented in this paper. With combination switch controls of three cascode devices in the driver stage, the power amplifier can achieve a variable power gain and output power (seven types). The power amplifier was fabricated in 0.35-μm standard CMOS process, and is able to deliver a power gain of 10.5~27 dB and an output P1dB (1-dB compression...
A charge sharing clock scheme is proposed to feed a 5-stage double charge pump circuit. By reusing the charges in charging or discharging the parasitic capacitance during the pumping process, dynamic power loss is able to be reduced by nearly a half. Under 1V supply, simulation results show a maximum 10% efficiency increase, and the ripple noise is also reduced by a half comparing to the conventional...
The method of using small-signal model to analyze jitter of the clock driver caused by thermal noise is presented. Multi-stage quasi-infinite load differential amplifier structure to effectively achieve low clock jitter is proposed. With transient noise simulation, jitter in the clock driver can be calculated. Through testing the SNR of ADC, The jitter of the designed clock driver in this paper is...
A novel frequency hopping technique is proposed to increase the efficiency in a switched-capacitor LED driver, based on analyzing the dependence of power loss on switching frequency. LEDs' load current is featured uniquely by jumping periodically from a constant value (20mA) to zero for dimming function. Developed on an improved VCO, the hopping technique makes the switching frequency vary discretely...
In this paper, a dual mode GaAs HBT power amplifier for LTE band I applications is present. The amplifier is designed to operate from 1.92 GHz to 1.98 GHz with 28 dB of gain, enough to work with transmitter chips with relative low output power. The amplifier deliveries 28 dBm of linear power at 3.4 V supply to satisfy the linearity requirement for the LTE application. To improve the average efficiency...
A novel 150V-BCD technology by using 14um thick epitaxy based on 0.35um standard CMOS process has been developed for LCD backlighting application. In the whole process with 24 steps, HV circuit block, including VDNMOS and LDPMOS with double resurf principle, and LV block are integrated together. Advanced deep trench isolation (DTI) technology with the breakdown voltage above 150V is firstly in place...
A driver for high-voltage (HV) single chip synchronous buck converters with a n-channel lateral double diffused MOS (nLDMOS) as power switches and a high speed low power level shifter is presented. Using a short time fast speed pull-down circuit, the level shifter realized high speed with a limited bias current. The circuit is implemented using UMC 0.5-μm 30V LDMOS process, and has been integrated...
In this paper a low swing driver-receiver pair (lhos-lp) for driving signals is proposed to optimize the energy dissipation and delay of global interconnect lines. The simulation, performed based on 1V 0.13μm CMOS technology with HSPICE, for signal transmission along a wire- length of 10 mm. The simulation results show lhos-lp is 18% and 14% better than other similar signaling schemes (lhos-db and...
Abstract A small footprint active clamp design with low voltage CMOS and high voltage BJT components in complementary BiCMOS process is proposed, analyzed by simulation and experimentally validated. The new clamp is composed from stacked NMOS driver to achieve appropriate voltage tolerance and power BJT. Both NPN and PNP- based versions of the clamp are compared to the stacked NMOS clamp.
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