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A Magnesium Doped Layer (MDL) under the 2-DEG channel and a Drain Metal Extension (DME) are proposed to provide a new degree of freedom in the optimization between breakdown voltage (BV) and specific-on-resistance (Ron-sp) in AlGaN/GaN HEMTs. The surface electric field of the proposed structure is distributed more evenly when compare to the MDL-only structure with the same dimensions. A breakdown...
We propose a new structure of Schottky rectifier, named trapezoid mesa trench MOS barrier Schottky rectifier (TM-TMBS). By 2D numerical simulations, both forward and especially better reverse I-V characteristics, including higher breakdown voltage and lower leakage current, were demonstrated and explained comparing to regular TMBS as well as conventional planar Schottky rectifier.
In this paper, a preparation process of PCRAM access-diode-array with proprietary intellectual property rights (PIPR) is shown simply. Then, Relationship between device parameters and diode performance, including drive-current, breakdown, especially disturb-current, which influences the data-veracity and reliability of PCRAM, is analyzed from the views of carriers distribution and parasitic PNP-BJT...
In this study, we investigated the electrical characteristics of p-channel transistor by changing the process sequence of P+ Source/Drain Ion Implantation (IIP) N2 annealing process in NAND Flash memory. For the case of changing the process sequence of N2 annealing, off-current of p-channel transistor was dropped sharply, and increase of the on current compared to the off current is not worse than...
A lateral power MOSFET with the extended trench gate is proposed in this letter. The polysilicon gate electrode is extended to the substrate, which improves the breakdown voltage (BV) and specific on-resistance (Ron). It indicates by simulation that the Ron of 1.86mΩ.cm2 with a BV of 174V in the proposed structure is nearly 53% less than the Ron of 3.96mΩ.cm2 with a BV of 126V in the typical structure.
An analytical model for high voltage Thin-film Silicon-On-Insulator (TSOI) lateral devices is proposed in this paper. A new Reduced SURface Field (RESURF) criterion is obtained for TSOI lateral devices with a lateral linear doping in the drift region. The optimum drift doping profile for TSOI lateral devices can be obtained from the new RESURF criterion. The analytical results are in good agreement...
A new Membrane PSOI High Voltage Device with a Buried P+ layer (MBP+ PSOI) is proposed. Breakdown voltage is only decided by lateral breakdown voltage because of the entire removing of silicon substrate under the drift region and breakdown voltage can be improved with increase of the length of the drift region. Introducing of P+ layer can effectively reduce specific on-resistance and silicon window...
A high voltage LDMOS on partial silicon-on-insulator (PSOI) with a variable low-k (relative permittivity) dielectric buried layer (VLKD) and a buried p-layer (BP) is proposed (VLKD BPSOI). In the vertical direction, the low k value enhances the electric field strength in the buried dielectric (EI) and the Si window makes the substrate share the voltage drop, which leads to a high vertical breakdown...
A novel 150V-BCD technology by using 14um thick epitaxy based on 0.35um standard CMOS process has been developed for LCD backlighting application. In the whole process with 24 steps, HV circuit block, including VDNMOS and LDPMOS with double resurf principle, and LV block are integrated together. Advanced deep trench isolation (DTI) technology with the breakdown voltage above 150V is firstly in place...
High breakdown voltage GaN HEMTs was developed for power electronics application. The device with source connected field plate (FP) was fabricated, which demonstrated perfect hard breakdown characteristics. A high breakdown voltage of 740V was obtained in air ambient while gate-drain spacing Lgd and FP length LFP equaled to 20μm and 2μm respectively. Specific on-resistance of the device was 14mΩ.cm...
This paper reviews the development of magnetoresistive random access memory (MRAM) with an emphasis on recent developments at IBM. MRAM is unique among nonvolatile memory technologies in having high endurance (actually unlimited) and high performance, though it is not the highest density technology. In the emerging form of MRAM that scales the best, spin-torque-transfer MRAM (STT-MRAM), control of...
A 700 V SA-LIGBT structure for high voltage applications is presented. An important feature is that the device has a good tradeoff among onset voltage, on-resistance and turn-off speed. This is realized mainly by two methods: large extent of P+ diffusion paralleled with N+ diffusion and the introduction of N-buffer layer in the anode. A robust SA-LIGBT is fabricated successfully with a breakdown voltage...
A capacitance coupling complementation silicon controlled rectifies (CCCSCR) for electrostatic discharge (ESD) protection application is proposed and verified in 0.5μm BCD process. Compared with traditional complementation silicon controlled rectifies (CSCR), the CCCSCR has a lower trigger voltage. The coupling capacitance, as a tunable trigger of SCR, can meet different protection application demands...
One way to increase the breakdown voltage in heterojunction field-effect-transistors (HFETs) on silicon substrate is to introduce a transition (buffer) layer made of a sandwich of thin AlN/AlGaN layers between the silicon substrate and the GaN well. The effect of this transition layer is to average out and, in this way, to reduce the local mechanical stress that appears between the silicon substrate...
A novel silicon-controlled rectifier (SCR) device with high-current low-voltage triggering characteristics is proposed to improve Electrostatic Discharge (ESD) immunity of the input gate oxide based on a standard 2-μm CMOS technology. The numeral simulation results shows that the device has a low trigger voltage (~11V) to effectively protect the gate oxide under ESD-stress conditions, and it also...
A driver for high-voltage (HV) single chip synchronous buck converters with a n-channel lateral double diffused MOS (nLDMOS) as power switches and a high speed low power level shifter is presented. Using a short time fast speed pull-down circuit, the level shifter realized high speed with a limited bias current. The circuit is implemented using UMC 0.5-μm 30V LDMOS process, and has been integrated...
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