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This paper describes a 64-entry × 32b 1-read, 1-write ported register file with measured 8.3GHz operation consuming 83mW, fabricated in 1.0V 32nm CMOS. Contention-free shared keeper circuits combined with variation tolerant dual-ended transmission gate write memory cells enable 300mV Vcc-min reduction and measured scalable near-threshold voltage operation to 340mV with energy efficiency of 550GOPS/W.
We propose circuit techniques for an 8T dual-port (DP) SRAM to improve its minimum operating voltage (Vddmin). Active bitline equalizing technique improves the write margin whenever a write-disturb occurs. This technique is applicable for both synchronous and asynchronous clock frequencies between ports. We designed and fabricated a 256 kb DP-SRAM macro using 28-nm low-power CMOS technology and achieved...
This paper presents a non-contact memory card and a host employing simultaneous data and power transmission through inductive coupling. Nested clover-shaped data coils are proposed for reducing interference from a power link. The host wirelessly tracks current consumption of the card and adjusts transmit power to improve power transfer efficiency. The prototype is implemented in 65nm CMOS. It achieves...
A method for characterizing dynamic SRAM stability using pulsed wordlines, is demonstrated in 45nm CMOS. Static read margins were observed to overestimate failures by up to 1000x while static write margins failed to predict outliers in dynamic write stability. Dynamic write stability was demonstrated to exhibit an enhanced sensitivity to process variations, and negative bias temperature instability...
A logic compatible embedded DRAM test macro fabricated in a 65nm LP CMOS process has a 512 cells-per-BL array architecture and achieves a random access frequency and latency of 667MHz and 1.65nsec, respectively at 1.1V, 85°C. The refresh period for a 99.9% bit yield was 110μsec. Key features include an asymmetric 2T gain cell, a pseudo-PMOS diode based current sensing scheme, a half swing write BL...
An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which is at least 4.3× higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth is reduced which results in 58% DRAM power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving of 54%.
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