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This study reports the effect of different barrier on Cu interconnect performance. A thin “enhancement” layer of Ru or Co film is deposited between a PVD Ta(N) liner barrier and a Cu seed layer to improve copper to barrier adhesion and copper gap fill. With the enhancement layer of either Ru or Co, no void is found in dual damascene structure with very thin seed. The electrical performance is improved...
The effects of structural design on the mechanical reliability of Cu/low-k multi-layer interconnects are investigated using finite element method. The Chip Package Interaction (CPI) was analyzed for a model of twelve wiring layers to calculate the energy release rate (ERR). The relations between the feature dimensions, such as copper interconnect width and low-k dielectric thickness, and the interfacial...
We present a methodology for capturing the intrinsic impact of both low-k dielectric stacks and packaging materials on the mechanical integrity of Cu/low-k interconnects. This drastically reduces the time and cost of sample fabrication and reliability tests and provides short-cycle feedback for both low-k and packaging materials development. Furthermore, this methodology is applicable for all types...
Packaging advanced silicon devices has become increasingly challenging because the effects of stresses exerted on interconnect structures during package assembly and operation are not well understood. In this study, a microprobe metrology system is used to assess the mechanics of these interconnect structures. This allows for a better understanding of the robustness of an interconnect design and the...
Chemical vapor deposited (CVD) Ruthenium liners and DirectSeedTM (DS) copper were used with advanced Electrofill processes to provide lower resistance wiring compared to results using CVD Ru and conventional physical vapor deposited (PVD) Cu seed for back end of line (BEOL) structures. Different annealing temperatures and simulated BEOL thermal stress builds were used to show the difference in resistance...
Through-silicon via (TSV) proximity is electrically evaluated for the first time based on a 130-nm CMOS platform. Transistors with TSVs in a two die stacking structure were successfully designed, fabricated and tested. With a minimum distance of 1.1 μm from a 5.2 μm diameter TSV, both PMOS and NMOS showed normal functionality. No performance degradation was identified compared to control cases without...
Lead-free flip chip package production solution for 40 nm technology node with aggressive ELK interconnect scheme and tight bump pitch of 150 μm is demonstrated. The use of LF bump and ELK dielectric in a same electronic component poses severe technical challenges due to the pronounced chip-packaging interaction in the system. In this paper, we reviewed the fundamental treatments to enhance the LF...
We present a modified Berman model that relates breakdown voltage distributions, from dual voltage ramp dielectric breakdown (DVRDB) test, to the distribution of time-to-fail (TTF) during constant voltage stress (CVS) conditions, assuming that dielectric failure behavior under a constant voltage stress follows the square-root E-model. The methodology presented in this work demonstrates a fast and...
We present results of a refined model that allows prediction of the influence of LER on the TDDB performance when scaling towards 20nm ½ pitch. The model is validated on 35nm ½ pitch state-of-the-art Cu/low-k interconnects, defined in a double patterning integration scheme, using wafer-level TDDB measurements and in-line post-CMP evaluation of both low-k space and parameters describing LER. The results...
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