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In this paper, we address the problem of scheduling and allocation for asynchronous systems, and present methods for performing both area-constrained and time-constrained design space exploration. Much of the recent work in this area has been adapted from synchronous approaches, and thereby suffers from the drawback of assuming discrete time (or a discrete approximation). Further, most existing approaches...
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This paper addresses the design of self-timed energy-minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a fully-decoupled latch controller has been developed, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which...
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Autonomous devices that are self-powered by extracting their energy from their environment are a new opportunity for monitoring purposes. A multi-energy sources and multi-sensors microsystem targeting autonomous wireless sensor node applications is presented. Since the available energy is not constant over time and due to very low harvested power levels, an efficient energy and power management strategy...
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Self-timed circuits present an attractive solution to the problem of process variation. However, implementing self-timed combinational logic is complex and expensive. In particular, mapping large function blocks into cell-libraries is difficult as decomposing gates introduces new signals which may violate indication. This paper presents a novel method for implementing any m-of-n encoded function block...
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The configurable routing in asynchronous FPGAs accounts for 80-90% of the total area and consumes 80-90% of the total power. This paper presents an asynchronous FPGA that applies two techniques to reduce power consumption. First, the routing is altered to use two-phase logic rather than four-phase logic. Second, enable (acknowledge) signals are voltage scaled such that the overall FPGA performance...
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This paper presents a systematic approach for microarchitectural exploration in pipelined asynchronous systems, with the goal of achieving a specified throughput target while minimizing a given cost function (based on energy, area, etc.). The method includes a general framework that (i) allows for a rich extensible set of microarchitectural transformations for improving throughput; and (ii) can handle...
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We describe an all-digital synchronizer that moves multi-bit signals between two periodic clock domains with an average delay of slightly more than a half cycle and an arbitrarily small probability of synchronization failure. The synchronizer operates by measuring the relative frequency of the two periodic clocks and using this frequency measurement, along with a phase detection, to compute a phase...
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Synchronous elastic circuits help synchronous designs tolerate computation or communication latencies, in a way similar to the asynchronous design style. The datapath is made elastic by turning registers into elastic buffers and adding a control layer that uses handshake signals and join/fork controllers. Join elements are the objective of two improvements discussed in this paper. The first one is...
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We present the circuit-level verification of a common arbiter circuit. To perform this verification, we address three issues. First, we present a specification for the arbiter and show how this specification amounts to a set of topological constraints on trajectories of the continuous model. Second, we show that computing bounding sets for these trajectories is complicated by stiffness of the differential...
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GasP circuit modules communicate handshake signals in two directions over a single state wire. The 2008 Infinity test chip demonstrated GasP in 90 nm CMOS operating at four giga data items per second, but revealed that state wires about 5000 lambda long retard operation by about 10%. Simulations reported in this paper show that GasP modules will tolerate surprisingly long state wires, albeit at reduced...
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Asynchronous circuits are well known for their intrinsic robustness to process, voltage and temperature variations. Nevertheless, in some extreme cases, it appears that their robustness is not sufficient to guarantee a correct circuit behavior. This limitation, which is caused by an analog phenomenon, appears when the transition slopes in input of C-elements become very slow. This paper describes...
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We present the design and implementation of an asynchronous high-performance IEEE 754 compliant double precision floating-point adder (FPA). We provide a detailed breakdown of the power consumption of the FPA datapath, and use it to motivate a number of different data-dependent optimizations for energy-efficiency. Our baseline asynchronous FPA has a throughput of 2.15 GHz while consuming 69.3 pJ per...
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Synchronizers play a key role in multi-clock domain systems on chip. Traditionally, improvement of synchronization parameters with scaling has been assumed. In particular, the resolution time constant (tau) has been expected to scale proportionally to the gate delay 'FO4'. Recent measurements, however, have yielded counter-examples showing a degradation of tau with scaling. In this paper we describe...
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Ultra low voltage operation promises to reduce power dissipation for wireless sensor network applications. Such ultra low voltage systems are likely to have many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold. Synchronizers are needed to interface among these domains. However, VDD scaling rapidly degrades synchronizers performance making them unsuitable...
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This paper presents a new design template and design flow for the implementation of data-driven asynchronous circuits. It relies on the use of edge-triggered flip-flops as the only storage elements, not only for the datapaths, but also for the control circuits; latches and C-elements that are common in many asynchronous circuit design styles are not required. The design template uses a two-phase handshake...
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