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A method has been defined to analyze the power dissipation of CMOS VLSI circuits by means of switch-level simulation. Random vectors are used as stimuli to the circuit to ensure vector-independentness. The method has been implemented using an existing mixed-level simulator. Results are described for a range of circuits, including a 20,000 transistor one.
This paper presents a speakerphone IC dedicated to handsfree telephone set applications. The main charateristic of this IC is that it can adapt itself to the electrical and acoustical environment by changing itself the gain of amplifiers and attenuators. This circuit can simulate closely a full-duplex handsfree system.
It has been shown that significant improvements to reliability and yield [1] can be attained with Error Correction Code (ECC) systems on DRAM chips. Placement of ECC systems on DRAM chips poses many practical problems, among which are increased access time and chip size. Described is a self-contained and selftimed on-chip ECC system imbedded in a high-speed 16-Mbit DRAM chip [2].
Two silicon bipolar analogue-to-digital converters are presented. The first device has 5-bit resolution and attains a sampling frequency of 1.6GSPS, whereas the second has 7-bit resolution and is capable of sampling at 1.0GSPS. Both devices are capable of operating with an analogue input up to their Nyquist frequencies.
New digital CMOS sea-of-gates architectures are being developed in order to increase the flexibility and density in generating micro-cells. The key feature of these sea-of-gates architectures is the absence of a row-oriented architecture. This paper presents two newly developed sea-of-gates arrays. In order to investigate the suitability of the developed arrays a multiplier circuit has been designed...
Analog counters are an attractive building block for Artificial Neural Networks circuits, either for weight representation or for statistical learning algorithms. We give two schemes for such counters, which feature different design trade offs. Model, simulation and test results are presented.
A CMOS circuit is proposed that emulates FitzHugh-Nagumo's differential equations using OTAs, diode connected MOSFETs and capacitors. These equations model the fundamental behavior of biological neuron cells. Fitz-Hugh-Nagumo's model is characterized by two threshold values. If the input to the neuron is between the two thresholds the output yields a sequence of firing pulses, if the input is outside...
A large and growing fraction of the power of modern VLSI chips is dissipated by the drivers of the external bus lines. The new Latch Bus driver system drastically reduces on-chip power dissipation and noise by employing a central driver chip which provides charge and discharge pulses and latches the information. The drivers of the selected bus station merely inhibit the charge process to produce a...
A specific circuit to solve ????= f(??), by finite-difference method, in 3D is presented. This circuit has been designed in CMOS-2??m technology, its area is about 0.7 square centimeter (100,000 transistors). Using this circuit to simulate potential distribution in silicon devices shows a drastic reduction of the computation time, 1.7 ??s per discretization node against 900 ??s by a software approach...
This article describes the architecture and design of a fully testable floating point processor. It performs 32-bits floating point arithmetic operations (addition, subtraction and multiplication) and it also performs integer-to-floating point, floating point-to-integer and inter-format conversions using either IEEE-P745 10.0, DEC-VAX or a two's complement format To enhance performances, the processor...
The paper describes the basic design methodology and the technological aspects involved in the integration of a high performance Prolog machine on silicon. The need of an efficient Prolog engine arises from the A.I. applications requiring great symbolic computation power. Currently available Prolog machines are implemented using a large number of boards. As a consequence they are expensive, cumbersome...
This paper presents the most recent results obtained at LIR on 128 ?? 128 mosaics with 50 ?? 50 ??m pitch operating in the 3-5 micron range at 77K. Readout circuit technology is described and electrooptical performances of 128 ?? 128 IRCCD arrays are presented. Moreover, typical pictures will illustrate these results.
A GaAs IC that performs clock and data regeneration functions for high speed fiber optic transmission systems is presented. This IC, in conjunction with a companion Si bipolar chip, can regenerate pseudo random NRZ data at rates up to 2.5 Gb/s with a sensitivity of 15 mV and uses a single -5.2 V ECL compatible power supply.
This paper reviews the design carried out to implement the IEEE P1149.1 boundary scan standard in the TSBC3 compiled portable library based on the GDT??/GENESIL?? tools. The advantage of this compiled approach is to provide a flexible set of boundary scan cells, including pads and Test Access Port (TAP) controllers. The boundary scan register is automatically assembled while creating the pad ring...
Bridging faults have been shown to be a major failure mode in CMOS IC's [SHE85]. A model that takes into account the different resistance values of the bridge is presented. This model is used to estimate the IDDQ range of values to evaluate the possibility of current testing of this fault [NIG90]. A simple circuit is used as an example. This methodology is demonstrated to provide a greater domain...
We present a 5th-Order Wave Digital Filter datapath designed using behavioural synthesis tools developed as part of the SARI project at the University Of Edinburgh. We use a simulated annealing based optimisation system to develop the execution plan for the filter, with a datapath synthesised using clique partitioning and a novel heuristically driven module selection mechanism. These tools may be...
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