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Current trends in desktop processor design have been toward many-core solutions with increased parallelism. As the number of supported threads grows in these processors, it may prove difficult to exploit them on the commodity desktop. This paper presents a study that explores the spawning of the dynamic memory management activities into a separately executing thread that runs concurrently with the...
Real-time systems have to complete the execution of a task within the predetermined time while ensuring that the execution results are logically correct. Such systems require scheduling methods that can adequately distribute the given tasks to a processor. Scheduling methods that all tasks can be executed within a predetermined deadline are called an optimal scheduling. In this paper, we propose a...
Program performance optimisations, feedback-directed iterative compilation and auto-tuning systems all assume a fixed estimation of execution time given a fixed input data for the program. However, in practice we observe non-negligible program performance variations on hardware platforms. While these variations are insignificant for sequential applications, we show that parallel native OpenMP programs...
A new parallel programming framework for DNA sequence alignment in homogeneous multi-core processor architectures is proposed. Contrasting with traditional coarse-grained parallel approaches, that divide the considered database in several smaller subsets of complete sequences to be aligned with the query sequence, the presented methodology is based on a slicing procedure of both the query and the...
One major issue in the design of multi-core systems is scheduling execution threads on the many cores. Heterogeneity complicates the issue given the different types of cores with various functionality and power requirements. In a large multi-core chip with long interconnect latencies, minimizing thread migration costs is essential in minimizing the power consumption and maximizing performance. In...
Recent developments in reconfigurable multiprocessor system on chip (MPSoC) have offered system designers a great amount of flexibility to exploit task concurrency with higher throughput and less energy consumption. This paper presents a novel fuzzy logic reconfiguration engine (FLRE) for coarse grain MPSoC reconfiguration that facilitates to identify an optimum balance between power and performance...
It is critical for the network-on-chip in embedded multi-core and many-core chips to be scalable while limiting power consumption. With the router power dominating the network's power, one way to achieve this goal is by the design of on-chip interconnection networks with small diameters and simple routing. Herein, we present a few new unicast on-chip networks for interconnecting the cores with diameters...
Work-stealing is the todays algorithm of choice for dynamic load-balancing of irregular parallel applications on multiprocessor systems. We have evaluated the algorithm's efficiency on a variety of workloads, including scatter-gather workloads, which occur in common algorithms such as MapReduce. We have discovered that work-stealing scheduling suffers serious scalability problems with fine-grained...
On-chip interconnection networks (OCINs) in many-core systems are key to the system's performance scalability. OCIN design constraints are governed by power, cost, latency, ease of routing, as well as others. As chips with 16 cores are around the corner, we focus on 16-core systems and consider 9 OCINs for 16-core MPSoCs. A key requirement of real time embedded systems is dependable timeliness. This...
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