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The paper presents a comprehensive study of Spice modeling for some key physical effects observed in a 65 nm CMOS process. STI-induced stress effect, well proximity effect, as well as HCI and NBTI reliability effects, which can not be neglected for technologies beyond 90 nm and must be properly modeled for accurate circuit simulations, are discussed in this study.
300 mm silicon single crystals have been grown using 24-28?? hot zones with the aid of numerical simulation. Mechanical strength of silicon seeds has been tested and a new style seed chuck developed. The damage layers during cutting, double side grinding (DSG) and double side polishing (DSP) have been investigated. The processing technology and the defects in silicon based materials such as silicon...
A new digital pressure-sensing device is presented. It employs the Micro-ElectroMechanical Systems (MEMS) technologies to form pressure sensing using PMOS ring oscillators to generate frequency which depends on the pressure-induced stress. The digital pressure sensor has several advantages. One of them is to convert the analog measurement of pressures into the frequency measurement. Compared to a...
Reliability of FinFETs is studied in this paper using the forward gated-diode generation-recombination (G-R) current. It is observed that the stress induced interface states result in the shift of the peak G-R current (??Ipeak) in the body current (Ib) versus gate voltage (Vg) characteristic, therefore the variation of interface states with stress time was calculated. In the hot carrier injection...
The negative-bias-temperature-instability (NBTI) is currently one of the most serious reliability issues in advanced CMOS technology. Specifically, the fast recovery of NBTI degradation immediately after stress is removed has recently become a hot topic. The major NBTI debates center on the responsible mechanism, the proper measurement method, and the possible impact on reliability. We show that the...
This paper focuses on the current fluctuation of post-hard breakdown thin silicon oxide films with thickness ranging from 3 nm to 5 nm. We characterize the post-degraded structure of silicon oxide films by analyzing current fluctuation spectra after hard breakdown.
We have compared the device performance of double-quantum-barrier charge-trapping memory of a TaN/Ir3Si-[HfAlO-LaAlO3]-HfON0.2-[HfAlO-SiO2]-Si device with single barrier non-volatile memory MONOS devices at close EOT. At 150??C under fast 100 ??s and low ??9 V P/E, the double-quantum-barrier charge-trapping device shows a 3.2 V initial ??Vth and 2.7 V 10-year extrapolated retention. This retention...
This study evaluated metal oxide semiconductor field-effect transistor (MOSFETs) with channel lengths/widths of 0.135/10, 0.45/10, and 10/10 ??m for both the n- and p- channel types used as sensing elements. The results show that the devices with channel lengths/widths of 0.45/10 and 10/10 ??m have flat saturation current. It suggests that there is a requirement for a device to have a channel length...
A novel DC-contact series RF MEMS switch using Al/Au composite membrane bridge is present. The warping problem of cantilever beam under residual stress is avoided by introduction of the slanting beam. Au-Au direct contact is achieved by using Al/Au composite membrane. The process is based on Borofloat?? glass substrate and resistance is used to isolate the crosstalk between the RF signal and DC driven...
The scaling of CMOS technology intensifies the interaction between design and process at 45nm or below, causing strong layout-dependent proximity effects. Photolithography, strain silicon engineering, and ion implantation are the primary causes of those effects, whose impacts to design can be mitigated via restrictive design rules and accurate modeling. A novel approach is proposed that seamlessly...
The piezoresistance model has commonly been used to describe mobility enhancement for low levels of process induced stress in CMOS technology. However, many reports show it failing at the high levels of strain needed for future technology generations. This is because an approximation is made which is only valid for very low stress levels. The piezomobility formulation removes this approximation in...
In the paper, the characteristics of thermal polyoxide grown on re-crystallized polysilicon by Metal-Induced-Crystallization (MIC) have been studied. The oxide quality can be improved due to smoother polysilicon/polyoxide interface and lower charge trapping by MIC re-crystallization. Furthermore, the polyoxide combined with CF4 plasma treatment, which exhibited better electrical characteristics such...
A poly-resistor 12-bit D/A converter is described in this paper. The D/A converter was processed in XC06 process technology. Since the trimming process isn??t used, the chip features the low cost. The linearity of the circuit was 0.3 LSB, and the settling time was 200 ns. The design and layout of the circuit was improved and optimized, and a novel cross layout scheme was especially adopted, thus resolving...
A novel capacitive temperature sensor based on multilayer cantilevers is presented. The top and bottom layers are metal and heavily boron doped Si, respectively. A combined SiO2/Si3N4 layer is utilized as the elastic dielectric layers of the sandwich multilayer cantilever. The operation principle of the structure is based on the effect of thermal expansion coefficient mismatch and the available physical...
Most integrated circuit ESD damages are caused by CDM stresses. This paper discusses CDM failure modes. The most common such failure is damage to the gate oxide in the MOS device. A new methodology that uses a gate oxide damage monitor and modified VFTLP testing is proposed for assessing CDM protection effectiveness and robustness in I/O circuits. A test structure for such an evaluation is also introduced.
With the navigation of ITRS, 32 nm technology node will be introduced around 2009. Scaling of CMOS devices from 45 nm to 32 nm node has come across significant barriers. In order to overcome these pitch-scaling induced barriers, it is demanded to integrate the most advanced process technologies into the product manufacturing. This paper will review and discuss new technology applications, which would...
The physical mechanisms of electron mobility (??e) enhancement by uniaxial stress are investigated for nMOSFETs with surface orientations of (100) and (110). From full band calculations, uniaxial-stress-induced split of conduction band edge (??EC) and effective mass change (??m*) are quantitatively evaluated. It is experimentally and theoretically demonstrated that the energy surface of 2-fold valleys...
Mobility enhancement by strain is a critical element in today??s CMOS technology, and enables continued performance scaling. By modulating fundamental material properties, various strained Si techniques boost device and circuit performance independent of geometric and power supply scaling. Challenges for strained Si in aggressively scaled technology demand new ideas and materials.
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