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The antenna effect is a phenomenon in the plasma-based nanometer processes that many charges are accumulated on metal wires which cause the degradation of gate-oxide. It also influences the chip reliability and manufacturing yield. Different with other methods based on Manhattan-architecture for the antenna avoidance, we propose the algorithm that combines jumper insertion and layer assignment (JILA)...
A novel dual direction SCR (DDSCR) ESD protection device is implemented in HJTK 0.18-??m CMOS process without deep N-well or T-well masks. Both parallel and anti-parallel metal routing method of multi-fingered DDSCR is investigated in this paper. It shows that metal routing in layout design plays an important role in the performance of multi-fingered DDSCR due to its symmetrical TLP I-V plot characteristics.
Deep sub-wavelength lithography, i.e., using the 193 nm lithography to print 45 nm, 32 nm, and possibly 22 nm integrated circuits, is one of the most fundamental limitations for the continuous CMOS scaling. Lithography printability is strongly layout dependent, thus routing plays an important role in addressing the overall circuit manufacturability and product yield since it is the last major physical...
In this paper, we develop a novel way to achieve Mesh+Local Trees (MLT) flow in encounter. By blending the advantages of CTS and ClockMesh into one clock design flow, MLT is guaranteed to have smaller skew, and further optimize mesh structure to achieve lower power. MLT provides real loading sum value instead of estimating for global Mesh structure; another feature of this flow is that it provides...
Graphic processing units (GPUs) have evolved to provide superb floating-point computing throughput, while parallelization will be the next major milestone for the development of electronic design automation technology. This work aims to harvesting the computing power for the VLSI physical design automation applications. We??re developing efficient, parallel computing kernels on the CUDA platform for...
The rectilinear Steiner minimum tree (RSMT) problem is one of the fundamental problems in electronic design automation. In this paper, we present a new heuristic algorithm called RSMT-MR for RSMT problem. There are two steps in the algorithm: MergeEdges and Refinement. Experiment results show that our algorithm is accurate and effective.
With the dramatic increase in size and complexity of systems on chip (SoC), there might be as much as hundreds of macro blocks and millions of standard cells integrated into a single chip. To facilitate signal routing and P/G network construction, one approach is to place macros around the boundary of chip and the remainder is used for arrangement of standard cells. To deal with such kind of placement,...
Static-random-access-memory(SRAM)-based field programmable gate arrays (FPGAs) consists of 50% ~70% routing resources. A simple programmable interconnect point (PIP) is a switch controlled by SRAM configuration cell connecting two wires. A novel traverse algorithm targeted for the detection of PIP open faults is proposed. Experimental results run on the Fudan design system (FDS) platform show that...
A multi-mode logic cell architecture in a tile-based heterogeneous FPGA is proposed, and a logic synthesis tool, called Vsyn, based on this architecture is presented. The logic cell architecture design and its synthesis tool development are strongly influencing each other. Any feature or parameter from one needs to be fully exercised and verified on the other. In this paper, we presented experimental...
In this paper, we present a multilevel hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15%...
Chemical-mechanical polishing (CMP) is one of the fundamental problems that should be considered for improving design for manufacturability (DFM) in routing. This paper presents a global routing algorithm, which is BCDRouter, to consider CMP. The algorithm uses the routing density of GRC to simulate the density of CMP, and reduces routing and congestion densities simultaneously. This will make the...
A method to integrate custom layout with ASIC back-end flow for high performance datapath design is introduced in this paper. It combines custom physical design techniques with conventional standard-cell based timing-driven back-end design flow. The results of two subchip design cases using this method for datapath circuits and implemented based on Fujitsu 90 nm process are presented, achieving advantages...
Network-on-chip (NoC), one of the most promising interconnection schemes for complex SoC design, presents large design space. Because the influence of different parameters on the performance of the NoC varies significantly, it is desirable to analyze and understand specific effect of these parameters on the overall performance in order to provide NoC designers guidelines to optimize their plans. In...
The cluster-based FPGA can significantly improve timing and routability. Packing is introduced in the CAD flow to pack logic elements into clusters. In order to reduce unnecessary connectivity within a cluster, sparse crossbar FPGA architectures are under investigation. This paper proposes a novel packing algorithm using direct graph searching method and connection gain function. Experimental results...
Different from older generation of FPGAs, routing resources of recent FPGAs are described by hierarchical general routing matrix (GRM). In this paper, we present a routing algorithm which utilizes routing resources more efficient for GRM based FPGAs. First, we build routing resource graph (RRG) by a bottom-up way, then we combine breadth-first search manner with A* directed by a certain proportion...
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