The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The material dependence of NBTI in SiON p-MOSFETs is studied using the UF-OTF IDLIN method. It is shown that the N density at the Si/SiON interface plays a very crucial role in determining the magnitude as well as the time, temperature and field dependence of NBTI. The relative contribution of interface trap generation and hole trapping to overall degradation is qualitatively discussed.
This article summarizes the history and progresses on our development of the Bipolar Field-Effect Transistor Theory (BiFET). The 2-Dimensional (2-D) rectangular geometry of the transistor (uniform in the width or Z-direction) is employed to decompose the 2-D equation into two 1-D equations which are parametrically coupled by the surface-electric-potential. This decomposition enables us to obtain the...
Precise two-dimensional current and capacitance modeling of short-channel, nanoscale multigate MOSFETs is presented. The model covers a wide range of operating regimes, geometries and material combinations. The modeling in the subthreshold regime is based on conformal mapping techniques. In moderate to strong inversion, we obtain self-consistent results based on the 2-D Poisson??s equation. The results...
We present a historic overview of the initial motivating ideas, original foundations, and subsequent development, of integration-based methods which are currently used to extract semiconductor device model parameters, as well as to assess devices?? and circuits?? non- linearity. To illustrate these methods?? capabilities, in this paper we review sample applications specifically focusing on two-terminal...
This article reviews integration-based model-parameter extraction methods for MOSFETs. It comprises three different methods that use the transfer characteristics measured under linear regime operation conditions. Additionally two other methods are included for extraction under saturation conditions. An integration-based method to evaluate the location of a maximum value of a given function is also...
The negative bias temperature instability (NBTI) of p-MOSFET has the greatest impact on the long term reliability of nano-scale devices and circuits. For several decades, NBTI research has been focused at the device physics level or on the characterization methodology, with little attention paid to the impact of NBTI on the performance of basic digital circuits. This paper discusses the effects of...
Intra-die fluctuations in the nanoscale CMOS technology emerge inherently to geometrical variations such as line edge roughness (LER) and oxide thickness fluctuations (OTF). A full 3-D statistical simulation is presented to investigate the impact of geometrical variations on the FinFETs performance. In this work, roughness is introduced by a Fourier analysis of the power spectrum of Gaussian autocorrelation...
This paper provides scattering matrix method to analyze the transport property in nanoscale MOSFETs. A unified mobility model with analytical expression is presented, which can cover the whole range from drift-diffusion to quasi-ballistic region. The inherent mobility reduction in MOSFETs with the shrinking of the channel length is extensively investigated from the theory and well agrees with the...
Off-state leakage current in a 65 nm partially depleted (PD) floating-body (FB) SOI technology is modeled and analyzed with emphasis on its drain-voltage dependence. Modeling accuracy of the off-state leakage current is highly dependent on modeling of parasitic currents, although their direct contribution to the leakage may be negligible in lower-power/high-performance technologies. The underlying...
This paper reviews the basic governing equations for a double-gate/gate-all-around (DG/GAA) MOSFET in a generic and unified description. Starting from generic Poisson solution and input voltage equation, a paradigm shift with ground-reference and source/drain by label is proposed, which is essential in formulating equations for DG FinFETs without body contact. The unified regional modeling (URM) approach...
This paper reports an analysis of the STI-induced mechanical stress-related breakdown characteristics of the 40 nm PD SOI NMOS device with a closed-form formula. As verified by the experimentally measured data, the 2D simulation results and the closed-form formula, the breakdown voltage becomes higher for the device with a smaller S/D length of 0.17 ??m due to the weaker function of the parasitic...
In this work, the impact of strain engineering on device performance and reliability for FUSI-gate SOI CMOSFET was investigated. With electrical measurement and reliability inspection, we found that there is similar enhancement on device performance, but different endurance on stressing induced device degradation for n/p MOSFET in respectively. Related noise analysis as well as charge pumping techniques...
Various aspects of the influence of scaling on stress engineering for 32 nm node are reviewed. Numerical simulations of width effect of embedded SiGe (e-SiGe) induced stress and the physical mechanism of stress memorization technique (SMT) are presented in this paper. A novel SMT scheme to further improve performance of PMOSFET is reviewed and demonstrated using numerical simulations.
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2 - 6 degree tilted off-axis (110) channel were reported. The transconductance of p-MOSFET with off-axis channel was significantly degraded compared with that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved compared with that of normal channel. The changes were larger than those observed...
By utilizing the fringing electric field from the control gate of cells in NAND flash memory string, the source/drain in the cells could be removed, which improves cell scalability and gives very positive effects. In this scheme, cells with underlapped S/D or localized buried oxide in the space shown more reasonable read current characteristics. For NOR flash memory, cells with recess channel structure...
Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20 nm-gate transistor. One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies. With 10 nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer...
In this study, the current driving capability of PN diodes and field effect transistors (FETs) for phase change memory (PCM) applications is investigated. To have a fair comparison, vertical gate-all-around (GAA) MOSFETs with similar cross-section as the PN diodes are selected for comparison. Through extensive 3-D device simulations have been performed based on existing experimental data from the...
We report on an AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) using thermal oxidation of electron-beam deposited aluminum as the gate dielectric. This novel dielectric deposition process is simple, and less expensive than electron cyclotron resonance (ECR) plasma oxidation of Al or atomic layer deposited (ALD) Al2O3. The X-ray Photoelectron Spectroscopy (XPS) Ols...
The author invented a trench-capacitor dynamic-random-access memory (DRAM) cell and applied the Japanese patent in 1975. The first trial development of trench-capacitor DRAM cell was presented in 1982 in 1-Mbit DRAM era. This might be the first attempt to utilize vertical wall of silicon substrate for metal-oxide-semiconductor (MOS) structure. Subsequent to this trial various kinds of vertical-channel...
In this paper, a 3.24 GHz~4.56 GHz wide-band voltage-controlled oscillator (VCO) fabricated in a 0.18 ??m 1P6M CMOS process is presented. This VCO is designed with a CMOS complementary-Gm oscillator topology, features two accumulation mode MOS varactors, and body-biased pMOSs. With 1.8 V power supply, when center frequency is 3.547 GHz, the phase noise is -119.2 dBc/Hz at 1 MHz offset. The oscillation...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.