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In this paper we present a methodology and its implementation for the design and verification of programming circuit used in a family of application-specific FPGAs that share a common architecture. Each member of the family is different either in the types of functional blocks contained or in the number of blocks of each type. The parametrized design methodology is presented here to achieve this goal...
In this paper, we have proposed a new high precision ramp waveform generator for low cost ADC test. With proposed test method combined with histogram analysis, an ADC can be easily tested on general digital testers. In our approach, we combine a traditional ramp generator with proper gain of operational amplifier (OPA) for ADC test. This new ramp generator structure can reduce the effect of output...
A novel bandgap reference for minimizing current-mirror mismatch is presented. In the proposed circuit, the small-signal current variations in the two current paths are self-compensated while in the conventional bandgap core they are multiplied. As a result, error caused by current-mirror mismatch has been much reduced in the proposed circuit. Moreover, the voltage variations caused by temperature...
The paper describes the newest layouts and the basic properties of pyroelectric single-element detectors which are built on the basis of lithium tantalate. The research aimed to develop detectors with a signal-to-noise ratio that is high as possible thereby ensuring optimum adjustment of the detectors to their planned application. Typical applications for the two new detector designs can be found...
Deep sub-wavelength lithography, i.e., using the 193 nm lithography to print 45 nm, 32 nm, and possibly 22 nm integrated circuits, is one of the most fundamental limitations for the continuous CMOS scaling. Lithography printability is strongly layout dependent, thus routing plays an important role in addressing the overall circuit manufacturability and product yield since it is the last major physical...
The scaling of CMOS technology intensifies the interaction between design and process at 45nm or below, causing strong layout-dependent proximity effects. Photolithography, strain silicon engineering, and ion implantation are the primary causes of those effects, whose impacts to design can be mitigated via restrictive design rules and accurate modeling. A novel approach is proposed that seamlessly...
This paper is concerned with the design of a high speed current steering DAC. Techniques to improve static precision are preserved while their negative influences on dynamic performance are suppressed. The prototype is implemented with the SMIC 0.13 ??m process. With an update rate of 700 Msamples/s, measurements show that the DAC achieves over 40 dB SFDR under a sampling rate of 700 Ms/s and consumes...
If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM. In order to optimize the yield of eSiGe process, a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level, therefore can be used as an early...
A new structure 288 ?? 4 CMOS time delay and integration (TDI) readout integrated circuit (ROIC) is presented in this paper. The TDI function is implemented using an integration and storage circuit array and a charge amplifier with the advantages of low power and compact layout. An experimental chip has been designed and fabricated in 0.5 ??m double-poly-three-metal CMOS technology. Bi-directional...
Chemical-mechanical polishing (CMP) is one of the fundamental problems that should be considered for improving design for manufacturability (DFM) in routing. This paper presents a global routing algorithm, which is BCDRouter, to consider CMP. The algorithm uses the routing density of GRC to simulate the density of CMP, and reduces routing and congestion densities simultaneously. This will make the...
In this paper, the development of a low drop-out voltage regulator with multiple enable controls was described. In circuit design, a lateral PNP transistor was used as a regulating transistor, and combined band-gap reference and feedback were adopted. The low drop-out voltage regulator was processed in 0.5 um BCD process technology. It has multiple enable control. The output current was 100 mA, the...
A poly-resistor 12-bit D/A converter is described in this paper. The D/A converter was processed in XC06 process technology. Since the trimming process isn??t used, the chip features the low cost. The linearity of the circuit was 0.3 LSB, and the settling time was 200 ns. The design and layout of the circuit was improved and optimized, and a novel cross layout scheme was especially adopted, thus resolving...
A method to integrate custom layout with ASIC back-end flow for high performance datapath design is introduced in this paper. It combines custom physical design techniques with conventional standard-cell based timing-driven back-end design flow. The results of two subchip design cases using this method for datapath circuits and implemented based on Fujitsu 90 nm process are presented, achieving advantages...
This paper presents an interface circuit for CMOS-MEMS gyroscope using integrated diode-rings. A brief introduction for the CMOS-MEMS integration technology [1] using high-ratio isolation trench will be introduced first. The integration system contains a Z-axis capacitive bulk silicon gyroscope and an interface circuits using diode-ring doing the first demodulation. A detailed analysis for the integrated...
As the CMOS scaling enters even deeper sub-wavelength lithography (i.e., 193 nm lithography for 45 nm, 32 nm, and even 22 nm nodes), tighter design and process integration is mandatory for the overall design and manufacturing closure. There are tremendous academic/industry research efforts on the manufacturability aware design, e.g., through hotspot detection/elimination during or post routing. But...
A Hybrid Waffle layout technique is introduced for the design of CMOS power transistors in integrated low voltage DC-DC converters. Comparing with conventional multi-finger layout scheme, the Hybrid Waffle layout scheme allows optimized trade-off between device on-resistance and metal interconnect resistance to minimize overall on-resistance. Interestingly, the reduced channel width per unit area...
A CMOS band-gap voltage reference with the characteristics of low offset and low supply voltage is presented in this paper. In order to reduce the effect of offset of operational amplifier, two feedback loops are introduced, so as to the factor of ??VBE is maximized meanwhile the factor of offset could be minimized. The area of layout is 1.5??1.3 mm2 with a 0.5 um CMOS process. Post-simulation results...
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