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In this paper, the transceiver which incorporates a PLL using a ring voltage-controlled oscillator (VCO), a phase interpolator (PI), the quarter-rate linear phase detector (PD) and an output driver with pre-emphasis is presented. The phase detector which uses a clock whose frequency is a quarter of the data rate and reduces the phase offset is proposed. The transceiver, implemented in a 0.18-mum CMOS...
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