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To detect problematic circuit behaviour, such as potential hazards and deadlocks, in a reasonable amount of time a technique is required which would avoid exhaustive exploration of the state space of the system. Many of the existing methods rely on symbolic traversal of the state space, with the use of binary decision diagrams (BDDs) and associated software packages. This paper presents an alternative...
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Self-timed rings are now considered as a promising solution for generating high-resolution timing signals. One of the main constraints for designing oscillators based on self-timed rings is to avoid burst oscillating modes and to produce uniformly spaced events in order to act as a periodic timebase. This paper presents a time-accurate model for self-timed rings based on a high-level behavioural model...
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This paper is a preliminary investigation in implementing asynchronous QDI logic in molecular nano-electronics, taking into account the restricted geometry, the lack of control on transistor strengths, the high timing variations. We show that the main building blocks of QDI logic can be successfully implemented; we illustrate the approach with the layout of an adder stage. The proposed techniques...
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Several asynchronous system design tools are based on syntax-driven translation of behavioral specifications (e.g., Balsa, Haste). While they provide rapid design times, the performance of the resulting implementations is typically limited, in part because specifications written by designers often have limited concurrency due to unpipelined operation and unnecessary sequencing. To overcome these challenges,...
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Due to aggressive technology scaling VLSI circuits have become more susceptible to transient errors. The associated reduction in supply voltages has decreased noise margins, causing system reliability to be reduced increasingly at a time when electronic systems are being used in ldquosafety criticalrdquo applications. Clock distribution issues as well as the demands for low power circuits have exposed...
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A new delay-insensitive data encoding scheme for global communication, level-encoded transition signaling (LETS), is introduced. LETS is a generalization of level-encoded dual rail (LEDR), an earlier non-return-to-zero encoding scheme where one of two wires changes value per data bit per transaction. In LETS, only one of N = 2n (1-of-N) wire changes value per n data bits per transaction. Compared...
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This paper presents the design and implementation of a low energy asynchronous logic architecture using sense amplifier-based pass transistor logic (SAPTL). The SAPTL structure can realize very low energy computation by using low leakage pass transistors and low supply voltage. The introduction of asynchronous operation in SAPTL further improves energy-delay performance and reliability without increasing...
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We present a technique to automatically synthesize heterogeneous asynchronous pipelines by combining two different latching styles: normally open D-latches for high performance and self-resetting D-latches for low power. Theformer is fast but results in high power consumption due to data glitches that leak through the latch when it is open. The latter is normally closed and is opened just before data...
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A complete family of untimed asynchronous 4-phase pipeline protocols is derived and characterised. This family contains all untimed protocols where data becomes valid before the request signal rises. Starting with a specification of the most parallel such protocol, rules are provided for concurrency reduction to systematically generate the family of all 137 related protocols that can be pipelined...
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The behaviour of asynchronous circuits is often described by signal transition graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving the set and reset covers for the state-holding elements implementing each output signal of the circuit. The derived covers must satisfy certain...
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As variability and timing closure become critical challenges in synchronous CAD flows, one attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. In this approach, each gate in an initial Boolean netlist is typically replaced by a robust dual-rail asynchronous template. However, these circuits typically have significant area and latency overhead...
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Two adaptation schemes based on on-chip measurement of failure rates have been proposed to reduce the effects of process, voltage, temperature and data rate variations on synchronizers on chip. One scheme is to select the best synchronizer out of a number to improve the synchronizer performance subject to process variation on chip. Compared to increasing the transistor size, this scheme can further...
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Asynchronous circuits are well-known for their benefits in terms of dynamic power savings, because asynchronous logic does not switch when inactive. Nevertheless, in deep-submicron technologies, leakage currents have become an increasing issue, and thus asynchronous circuits need to focus on static power consumption reduction. In this paper, we propose an innovative way to detect incoming asynchronous...
