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This paper presents a new verification system for FPGA based designs described in the JHDL hardware description language. The method consists of performing hardware emulation of designer selected blocks in a co-simulation environment. Although JHDL has a Hardware execution mode it does not provide a fine control of which blocks have to be executed in Hardware and it is based on Xilinx readback technology...
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The benefits of high performance computing (HPC) can be seen in a wide range of applications. From science and medicine to industries as diverse as oil exploration, financial, and entertainment, access to cost-effective HPC is becoming a critical part of our national infrastructure. Although exponential semiconductor advances are giving computational scientists faster computing speeds, applications...
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We present a low-cost stereo vision implementation suitable for use in autonomous vehicle applications and designed with agricultural applications in mind. This implementation utilizes the Census transform algorithm to calculate depth maps from a stereo pair of automotive-grade CMOS cameras. The final prototype utilizes commodity hardware, including a Xilinx Spartan-3 FPGA, to process 320times240...
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In this paper we present a configurable digital signal processor synthesis (CPS) System that produces a library of high-performance processors wherein each processor executes a specific digital signal processing (DSP) algorithm. Each processor contains a small instruction set and implements a particular application. These algorithm specific DSPs (ASDSPs) are used to alleviate bottlenecks in software...
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In the present paper the background generation and motion detection algorithms, which are of key importance for the implementation of video detection, have been presented. A modification of the background generation algorithm, essential for proper algorithm functioning at medium and high road-traffic conditions, has been proposed. Algorithm adaptation for the implementation in reprogrammable device...
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Dimensionality reduction or feature extraction has been widely used in applications that require to reduce the amount of original data, like in image compression, or to represent the original data by a small set of variables that capture the main modes of data variation, as in face recognition and detection applications. A linear projection is often chosen due to its computational attractiveness....
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Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. This paper presents rapid prototyping results of a bandpass filter as a sample analog circuit using our floating-gate based large-scale FPAA. A major source of parasitics introduced during the circuit mapping process is interconnect...
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This paper introduces a parameterisable, application and platform-independent, hybrid memory sub-system for custom hardware. This memory sub-system consists of a scratchpad memory (SPM) and a custom parallel cache, which exploits data re-use effectively in spite of data dependence. The cache is capable of exploiting spatial locality of memory accesses in two dimensions, making it ideal for video applications...
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A formal methodology for automatic hardware-software partitioning and co-scheduling between the P and the FPGA has not yet been established. Current work in automatic task partitioning and scheduling for the reconfigurable systems strictly addresses the FPGA hardware, and does not take advantage of the synergy between the microprocessor and the FPGA. In this work, we consider the problem of co-scheduling...
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High power consumption is a constraining factor for the growth of programmable logic devices. We propose two techniques in order to reduce power consumption. The first is a technique for creating contexts. This technique uses data-dependent circuits and wire sharing between contexts. The second is a technique for switching the contexts. In this paper, we evaluate the capability of the two techniques...
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The distinct advantage of SRAM-based Field Programmable Gate Arrays (FPGA) is their flexibility for configuration changes. But this opens up the threat of intellectual property (IP) theft since the system configuration is stored in easy-to-access Flash memory. High-end FPGAs have already been extended with symmetric-key decryption engines used to load an encrypted version of the configuration that...
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This paper describes the integration and performance of a multi-stream cipher core with a uClinux Microblaze based reconfigurable system-on- chip that uses the Open Crypto framework. This allows applications to access the multi stream cipher core via kernel space calls.
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While scientific applications in the past were limited by floating point computations, modern scientific applications use more unstructured formulations. These applications have a significant percentage of integer computation - increasingly a limiting factor in scientific application performance. In real scientific applications employed at Sandia National Labs, integer computations constitute on average...
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This paper describes a novel architecture for the hardware implementation of non-linear multi-layer cellular neural networks. This makes it feasible to design CNNs with millions of neurons accommodated in low price FPGA devices, being able to process standard video in real time.
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Augmented reality (AR) is a highly interdisciplinary field which has received increasing attention since late 90s. Basically, it consists of a combination of the real scene viewed by a user and a computer generated image, running in real time. So, AR allows the user to see the real world supplemented, in general, with some information considered as useful, enhancing the users perception and knowledge...
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This work explores a hardware design alternative and a cost assessment of an FPGA-based brute force attack against the challenge RC5-72. The aim is to develop an alternative to software-based solutions for distributed.net. Hardware platforms, particularly reconfigurable hardware, can offer significant cost, flexibility and performance advantages, while significantly reducing environmental energy costs...
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We present a dynamic dataflow execution model, called the aggregated hierarchical abstract hardware architecture (or AHAHA), for use in FPGA based applications. High level language implementations targetting FPGAs use either handshaking or control-path solutions to schedule computations. Among the handshaking variety are the Compaan VHDL Visitor; the control-path solution uses a simplified form of...
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Traditional FPGA education either involves a physical laboratory room with workstations connected to individual FPGA experimenter boards or simulation platforms. Physical labs are expensive to maintain and require substantial floor space. In addition, students need to be physically present in the laboratories to access the FPGA boards. On the other hand, it is often the case that simulation platforms...
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BLASTP is the most popular tool for comparative analysis of protein sequences. In recent years, an exponential increase in the size of protein sequence databases has required either exponentially more runtime or a cluster of machines to keep pace. To address this problem, we have designed and built a high-performance FPGA-accelerated version of BLASTP, Mercury BLASTP. In this paper, we focus on seed...
