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A new simple ultra-wideband (UWB) monocycle pulse generator based on step recovery diode is presented. This pulse generator uses nonlinear components with a single power supply and microstrip transmission lines. It is made up of three parts : a Gaussian pulse generator, an impulse-shaping network, and a monocycle-pulse forming circuit. The proposed circuit allows to generate ultra-short Gaussian monocycles...
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A new method of nonlinearity reduction for accuracy improvement in the displacement measurement system based on the heterodyne Doppler-interferometry method is presented. A two-frequency He-Ne laser at 633 nm central wavelength and 152 MHz free spectral range is used as a source. The electrical induction and unwanted electromagnetic leakage between the reference and measurement paths produce nonlinearity...
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This paper presents a multi-channel audio equalizer which hosts both a multiband filterbank module and an analog-to-digital converter (ADC) module. Each module is designed to minimize the space occupation of the ASIC. The multiband filterbank module is designed to utilize a time shared multiplier. The time shared multiplier effectively reduces the gate numbers required in implementing the multiband...
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Recent advances in vision system integration allows to design new integrated sensors which are able to achieve complexes tasks. The 'Cyclope' project aims to develop a novel integrated sensor for real-time 3D reconstruction. It includes an active vision sensor, a digital centralized processing architecture and a communication block. This sensor is designed to obtain a monolithic integrate vision system...
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In integrated all-digital FPGA based communication systems bit synchronization is a fundamental operation for the best symbol detection. In this paper a highly flexible early-late gate implementation is proposed. It is optimized for low resource consumption in FPGA implementations.
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Third generation communication systems offer variable spreading factor and multiple codes per user. Hence, the receiver architecture should be configurable to meet varying needs and should consume as little power as possible. To achieve this, different types of RAKE receivers have been designed and implemented. In this paper, we propose a new architecture of the RAKE receiver, intended to reduce area...
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In this paper, CMOS analog-to-digital converter (ADC) with a 6-bit 100 MSPS at 1.8 V is described. The architecture of the proposed ADC is based on a folding type ADC using resistive interpolation technique for low power consumption. Further, the number of folding blocks (NFB) is decreased by half of them, compared to the conventional ones. With the clock speed of 100 MSPS, the ADC achieves an effective...
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In this paper we present a design for an efficient FPGA implementation of a color space converter in video compression. The proposed architecture is based on distributed arithmetic principles has been implemented on the Xilinx Virtex-2000E FPGA using a hybrid design approach combining Handel-C and VHDL. Maximum optimization of performance metrics including frequency and power has been achieved by...
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In this work, the practical improvements in latency for division over GF(2m) are explored. Elliptic curve cryptography (ECC) hardware accelerators often require low-latency, flexible divider architectures for implementation in FPGA technology. Architectures based on the extended Euclidean algorithm (EEA) are implemented using a digit-serial approach, and the design space is explored using empirical...
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For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. For each new generation of process technology the thickness of the transistor gate-oxide will be reduced. This will increase charge leakage in FGMOS circuits and it is therefore necessary to introduce techniques to keep...
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One of the main objectives of transaction level modeling is to create models at high level of abstractions in order to obtain acceptable simulation performance. However, the use of simulation engines based on event driven simulation and communication through complex channels wipe out this advantage. In this paper we show how to regain this advantage by internally transforming the model while keeping...
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In SoCs (system-on-chip) with mixed-signal cores, both the functional behavior and the production tests should be simulated at top level before tape-out. The use of behavioral models for the analog and mixed-signal cores enables simulation of the whole signal path including the analog inputs or outputs of the mixed-signal cores. Since many SoCs are described in the Verilog HDL (hardware description...
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This paper presents the design for high speed flat-plane receiver circuit application. Due to the differential transmission technique and the low voltage swing, mini-LVDS (low-voltage differential signaling) allows high transmission speeds and low power consumption at the same time. High transmission speed with the minimum common-mode and differential voltage at the input for mini-LVDS application...
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The circuit proposed in this paper allows to generate a sub-1V 50 nA current reference. By changing the inversion mode of two transistors, the original Oguey's structure becomes compliant with ultra low voltage requirements, while preserving the topology inherent simplicity, guarantee of low cost. Furthermore, the use of EKV2.0 MOS model involves an inversion level free study. As a consequence, supply...
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This paper presents the concept and the design of a new architecture for microfluxgate sensors. An innovative low-pass architecture based on pulsed excitation is presented, with a SigmaDelta-based closed-loop measurement circuit including digital and semi-digital filters. While the total power consumption is reduced to about 20 mW, it also allows a power/resolution tradeoff for a digitally-controlled...
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This paper presents a new high speed voltage-mode max-min method for fuzzy application. In the proposed circuits, a differential pair is employed to choose the desired input. In addition to high speed, high precision and simple expansion for multiple inputs are the main advantages of this method. HSPICE simulation results show that the proposed circuit has maximum of 1% error at 100MHz.
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A new methodology for the design of two-stage cascode-compensated operational amplifiers (opamps) is proposed in this paper. It specifies proper open-loop circuit-level parameters regarding the desired bandwidth and closed-loop stability. As the effect of the zeros of the open-loop transfer function has been taken into account, the presented methodology becomes more accurate than previous methodologies...
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The periodically time-varying two-terminal network at a steady state may be described with a circular parametric operator. Within the domain of discrete time, such operator takes the form of a real element matrix. A circular parametric operator may be transformed into the frequency domain. In this version, the quantitative assessment of mixing and generating of harmonics of input and output signals...
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This paper presents a hybrid evolutionary algorithm to synthesize the resonator filters of an arbitrary topology. In this approach the structure space is explored concerning predefined small building-blocks having specific functionalities (resonator or coupling) and rules for structural restrictions. The method used 2D representation, proposing new strong genetic operators and combining a biobjective...
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A real-time address tracer provides designers a realtime monitoring capability which is the kernel of a dynamic debugging system for any embedded system such as the ARM7TDMI. According to the localities of programs, in our previous version, we have provided an effective compression method, which usually uses only 8 to 32 entries (32 bits each entry) of table, a simple counter and low cost hardware...
