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A long chain of inverters and wire segments will amplify clock jitter and drop timing pulses due to intersymbol interference. We present a jitter attenuating buffer based on surfing techniques. Our buffer circuit consists of a few inverters with variable output strength that implement a simple, low-gain DLL. Chains of these surfing buffers attenuate jitter making them well suited for source-synchronous...
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Synthetic biology uses engineering principles to design circuits out of genetic materials that are inserted into bacteria to perform various tasks. While synthetic combinational Boolean logic gates have been constructed, there are many open issues in the design of sequential logic gates. One such gate common in most asynchronous circuits is the Muller C-element, which is used to synchronize multiple...
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As system-level interconnect incurs increasing penalties in latency, round-trip cycle time and power, and as timing-variability becomes an increasing design challenge, there is renewed interest in using two-phase delay-insensitive protocols for global system-level communication. However, in practice, when designing asynchronous systems, it is extremely inefficient to build local computation nodes...
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VLSI systems are often constructed from a multitude of independently clocked synchronous IP blocks. Unfortunately, while a synchronous design style may produce efficient block level implementations it does little to support their composition. The addition of asynchronous interfaces to each synchronous block is one way to simplify and strengthen their integration. Asynchronous interfaces allow blocks...
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A simple scheme for single rail asynchronous data transmission and signaling relying on the management and transfer of conserved quantities is presented. The conserved quantity is dependent on the kind of logic family used: mass for fluidic logic, charge for CMOS logic, and flux for superconducting flux quantum logic.
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Robots not only can be useful, but also can entertain. From the robot fountains at Bellagio to humanoid figures and Jurassic park dinosaurs, Sarcos has applied new technology to make things move in complex and entertaining ways. Major improvements in the cost and reliability of sensors and actuators have made these projects possible; improvements that also apply to more practical work in robots for...
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This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-performance error correction codes used in applications where maximal information transfer is needed over a limited-bandwidth communication link in the presence of data corrupting noise. Specifically we designed an asynchronous...
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The "Vortex" processor is a general purpose CPU with a novel architecture and instruction set. The primary feature of the Vortex architecture is many parallel function units which communicate through a central crossbar, instead of a traditional register file. Instructions are fetched in parallel by cache lines, as in a VLIW processor, but any data or structural dependencies are resolved...
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For today's SoC designer, on-die variation, clock distribution, timing closure, and power concerns confront the desire to get products to market quicker. Each new process generation makes the challenge greater as process skews, complexity, and frequency become more onerous. This is particularly true for signals that have to travel across larger portions of a chip such as clocks and buses. In this...
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FDR (failures-divergences refinement) is a tool for verifying properties of processes expressed in a machine-readable dialect of CSP (CSPM). This paper shows how to model asynchronous logic blocks as processes in CSPM and how to verify them using FDR: processes abstract away from the speed of the blocks; multi-way synchronization facilitates the modelling of isochronic forks; receptiveness is formalised...
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Microprocessors are employing higher levels of system integration for both higher performance and lower system cost. In doing so, problems that used to be apparent inter-device are now found intra- processor. The integration of the processor core with other units such as the north bridge often increase the number of clock domains within the device. In addition, the frequency of the external interfaces...
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In this paper, a systematic and automated methodology is proposed for decomposing an asynchronous burst-mode (BM) controller into smaller sub-controllers, where each resulting sub-controller is activated on a communication channel. The proposed approach consists of a new decomposition algorithm, control micro-architecture and inter-controller communication protocol. This method has also been broadened...
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We present a method of building pseudorandom bit sequence (PRBS) generators using coupled asynchronous FIFO rings. A traditional PRBS generator using a linear feedback shift register (LFSR) can only generate a single maximal-length pattern with a fixed period. Our proposed FIFO implementation allows a single circuit to produce many different patterns of different periods, all of which are maximal-length,...
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Timing issues are a major concern in the design of high performance synchronous, asynchronous circuits and GALS. Investigations into the causes of many timing problems cannot be satisfactorily undertaken using external equipment due to its remoteness from the source of the potential problem; this necessitates the development of on-chip time measurement circuitry. Current techniques have the capability...
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Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous tool flows, they introduce large area and speed overheads. This paper proposes...
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Designs which require a phase relationship between two signals to be maintained along a link benefit from the use of repeaters which actively regenerate this relationship. This paper discusses some implementations of phase-regeneration circuits and attempts to introduce the reader to the issues encountered in the design of such circuitry. The paper proposes various design solutions for the dual-rail...
