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In this work, we present for the first time experimental evidence for the reduced gate tunneling current density in narrow FinFET structures compared to quasi-planar very wide-fin structures. This reduction is observed for both nand p-channel and is found to be larger for HfO2 than for SiON. For a given gate dielectric, the above reduction depends on the fin width. For SiON with an equivalent oxide...
A novel and uniform channel program and erase method is presented to replace the FN tunneling operation for SONOS cells in NAND architecture. The proposed operation utilizes substrate transient hot electron (STHE) injection and substrate transient hot hole (STHH) injection for programming and erasing, respectively. Gate bias polarity can control whether hot electrons or hot holes are injected into...
A numerical study of carbon nanotube field effect transistors is presented. To investigate transport phenomena in such devices the non-equilibrium Green's function formalism was employed. Phenomena like tunneling and electron-phonon interactions are rigorously taken into account. The effect of geometrical parameters on the device performance was studied. Our results clearly show that device characteristics...
In this paper, we analyze the experimental SILC statistical data at low stress reported in (Driussi et al., 2005) . To this purpose we developed an analytical physical model to study the statistical distribution of the TAT current due to single and multiple traps in the gate oxide of a floating gate memory cell. We modeled also the generation dynamics of conductive percolation paths due to more traps...
A novel asymmetric Schottky tunneling source MOSFET is proposed in this paper. The main feature of this device is the concept of gate controlled Schottky barrier tunneling at the source. The STS MOSFET was fabricated using conventional processes combined with present NiSi technology. The device shows excellent short channel immunity, compared to conventional SOI MOSFETs. This improves the scalability...
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