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For the scaling of embedded floating gate (FG) memories towards the 45nm CMOS generation and beyond, a reduction of the program and erase voltages is required. A solution is the use of high-k inter-poly dielectrics (IPD) to increase the coupling of the control gate (CG) to the FG. Compared with standard IPD materials like oxide-nitride-oxide (ONO), materials with higher k-values give a better coupling,...
This work describes a concept of an isolated high-voltage (HV) n-channel LDMOS transistor, which can be used as a high-side switch instead of a HV PMOS transistor. HV n-channel LDMOSFETs for 120V applications (blocking voltage over 150V) were used in the study. The devices were fabricated in a 0.35 mum CMOS-based HV technology. Hot carrier stress experiments (under gate voltage VGS = 10V and drain...
An analysis of a novel electrically programmable element called an "active fuse" is presented. The device was manufactured in a 65nm CMOS SOI technology. The active fuse is implemented in the SOI silicon film and thus, unlike conventional polysilicon (poly) fuses, remains CMOS compatible with future gate stack materials. The authors show that an active fuse has electrical properties very...
The reliability of recess-channel gate (RG) cell transistor under positive bias Fowler-Nordheim (F-N) gate stress and gate-induced drain leakage (GIDL) stress was investigated. RG cell transistor was found to be more degraded by the F-N gate stress than the GIDL stress due to the gate oxide thickness profile of the RG structure. The oxide thickness along the sidewall plane is a critical factor determining...
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