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Gate induced drain leakage (GIDL) characteristics were investigated with the recessed channel array transistor (RCAT) for DRAM, using the elevated source drain (ESD). The lower doping concentration of a source-drain region in the ESD structure reduces the electric field, which reduces drain leakage current and also the fluctuation of leakage current. These reductions can enhance the data retention...
In this paper, we present the characterization and analysis of fixed-pattern noise (FPN) in CMOS image sensor (CIS) pixels fabricated in CMOS 0.18-mum process. The experimental results demonstrate that the dark signal degradation of pinned 4T CIS is mainly due to the dark current generated from the transmission gate (TG) instead of the photodiode (PD). From our investigations of gate voltage/charge...
A novel and uniform channel program and erase method is presented to replace the FN tunneling operation for SONOS cells in NAND architecture. The proposed operation utilizes substrate transient hot electron (STHE) injection and substrate transient hot hole (STHH) injection for programming and erasing, respectively. Gate bias polarity can control whether hot electrons or hot holes are injected into...
A novel vertical channel nonvolatile memory cell with oxide-nitride-oxide-nitride-oxide (ONONO, dual nitride trapping layers) dielectrics stack is proposed and experimentally demonstrated for the first time. Compared with the conventional planar NROM cell, since the cell area of the proposed vertical structure is independent of the gate length, the VDNROM structure can relax the limitation of the...
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