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The paper reports a novel dual metal gate (MG) integration technique for gate-first CMOS process by intermixing (InM) of ultra-thin metal and metal nitride (MNx) films at high temperature together with source/drain (S/D) activation process. In this process, a thin (~2 nm) TaN buffer layer is used to prevent the gate dielectric being exposed during the metal etching process. Work function (WF) of TaN...
Long channel Ge FETs and capacitors with CeO2/HfO2 /TiN gates were fabricated by photolithography and gate wet etch. Rare earth CeO2 in direct contact with Ge was used as a passivating layer producing lowest Dit values in the mid 10 11 eV-1cm2 range. HfO2 cap reduces leakage and improves equivalent oxide thickness scaling of the whole gate stack. The p-FETs show exceptionally high ION/I OFF ratio...
A technique has been developed to fabricate transistors using a continuously scaled 0-2.5 nm SiO2 interface layer between a silicon substrate and high-κ dielectric on a single wafer. Transistor results are promising with good mobility values and drive current. The slant etching process has no detrimental effect on the electrical characteristics of the Si/SiO2 interface. This technique provides a powerful...
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