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Replacing the tunnel oxide of non-volatile memories by a high-k dielectric is addressed in this paper. This work reports in its first part an experimental study of conduction and trapping in Al2O 3 layers. The experimental data of these layers is then integrated in a novel endurance model suitable for flash memories with high-k tunnel oxide. Simulation results show that low (+8/-7V) operating voltages...
For the scaling of embedded floating gate (FG) memories towards the 45nm CMOS generation and beyond, a reduction of the program and erase voltages is required. A solution is the use of high-k inter-poly dielectrics (IPD) to increase the coupling of the control gate (CG) to the FG. Compared with standard IPD materials like oxide-nitride-oxide (ONO), materials with higher k-values give a better coupling,...
Continued shrinkage of floating gate devices requires scaling of the tunnel and/or interpoly dielectrics. This leads to increasing leakage currents that jeopardize the nonvolatile memory retention requirements. High-k materials are natural candidates to enable further scaling of the tunnel/interpoly dielectrics. In this paper, we present an analysis of the defects in Al2O3-based stacks. It is found...
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