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In summary, the implementation of a Co(W,P) cap only on the Cu lines is able to improve the dielectric breakdown performance in Cu/low-k interconnects. This is due to the elimination of the weak interface between the cap and the low-k dielectric. However, the thickness of the Co(W,P) cap needs to be optimized in order to fully benefit from the breakdown improvement while maintaining its efficiency...
Increased packing density and reduced device size leads to increase in the back-end related delays. This happens as a result of increase in the metal resistance due to decreased line-width and increased capacitance due to a higher density of the interconnects. To minimize the impact of interconnect related delays (RC delay) the semiconductor industry had to, as a first order change, look for metal...
In this paper, inter layer dielectric characteristic ramped voltage breakdown (VBD) performance of multiplayer Cu/SiOC interconnect was studied. The results showed that the breakdown reliability is highly process-related. Some dominating factors, such as via etching process, integration scheme used and Cu/dielectric interface etc., were discussed and proposed to improve breakdown reliability performance
In this study, we propose a LSC technique that using SiN capping layer deposition with high mechanical stress on single poly-Si gate. In addition, nMOSFETs with thicker poly-Si gate (220 nm) can also increase tensile strain in the channel region compared to that of the thinner (150nm) poly-Si gate structure. Furthermore, size dependence of nMOSFETs with SiN capping layer is also studied and compared...
Two phases during the P/E cycling of 0.18mum SONOS are observed using a combined charge pumping method to extract the trapped charge distribution: holes accumulation at the initial term, and electrons accumulation after long term cycling. Better endurance characteristic is obtained through optimization to P/E condition and process technology
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