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The evolution of laser sources has led to the advent of new laser-based techniques for failure analysis. The pulsed OBIC (optical beam induced current) technique is one of them, which is based on the photoelectric laser stimulation of the device under test (DUT) at a micrometric scale. The suitability of this technique to localize failure sites resulting from electrostatic discharges (ESD) has previously...
A proposed method for failure analysis and debugging of electrostatic discharge protection in VLSI circuits is presented, based on low-energy non-destructive emulation of real ESD stress. It allows on-die current and voltage measurements during stress, providing a direct and clear conclusion about the proper functioning of the protection method, or a reason for failure
Electrical and SEM analysis of gate-silicided (GS) and gate-non-silicided (GNS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism switches away from classical drain-to-source filamentation when the silicidation between the silicide-blocked drain/source and the polysilicon gate is avoided. For 2.5V thick oxide devices, drain-to-substrate junction shorting was observed, whereas,...
As semiconductor process technology rapidly develops into deep-sub-micron or nanometer regime, the feature size of semiconductor devices continues to shrink down. As a result, the defect being able to cause a device malfunction is also becoming smaller and smaller, and even certain defect is invisible with high-resolution SEM or TEM. It makes conventional physical failure analysis (PFA) face a great...
The adoption of SOI structure into 90 nm IC devices makes the characterization very challenging. TEM characterization becomes more critical, challenging and indispensable in the failure analysis of such devices. To illustrate the application of TEM in this area, several unique examples including both cross-sectional and planar analysis are given here
Failure analysis (FA) is key in root cause identification for any problem solving journey. Diagnosis given provides insights on mechanisms by which failures occur. This helps in determining factors that lead to the failure and consequently the root cause, thus easier to provide corrective actions. In mid June 2004, a sudden increase in test fall-outs was encountered. Several devices from different...
This paper describes a new dc-coupled laser induced detection system for fault localization in microelectronic failure analysis. This method removes artifacts inherent in ac-coupled detection systems and is capable of producing an accurate mapping of the laser induced resistance change of the devices without signal attenuation. This method is also capable of localizing large area faults without signal...
Optical techniques (light emission and laser stimulation techniques) are routinely used for precise IC defect localization. At the early stage of an analysis, choosing the right technique is an increasingly complex task. In some cases, one technique may bring value but no the others. Using an 180nm test structure device we present results showing the complementary of emission microscopy (EMMI), time-resolved...
The purpose of this paper is to present a novel deductive methodology, which is accomplished by applying difference analysis to nano-probing technique. This methodology would like to resolve the erratic device with a tailing failure or puzzling feature, but not only to check if the suspect had incorrect characteristic or mismatched transistor parameters
In this paper, systematic pair bit failure is analyzed in failure bit map of deep-submicron CMOS technology. Tungsten plug corrosion in contacts of stacked contact/metal/via structure is observed from careful analysis of failure bit. Then, some experiments have been carried out to identify and resolve this corrosion failure. This corrosion reaction occurred through the void space, which is formed...
Surface charging is encountered in the study Auger electron spectroscopy of non-conducting surfaces. In this paper, two case studies of (i) Au-pad of packaged die unit and (ii) floating Al-pads of patterned wafer were presented. Surface charging was noticed in both the samples and it was not possible to eliminate the effect with convention charge reduction methods. Two FIB-based methods of charge...
The importance of understanding asymmetrical behaviour in SRAM has increased as the technology node shrinks below 100 nm. Single bit failure can possibly be caused by the malfunction of any of the six transistors in a standard SRAM cell. In order to understand the asymmetrical behaviour in advanced nano SRAM devices, nanoprobing is introduced to perform transistor level fault isolation prior to attempting...
The paper could limit itself to repeat the complaint that originated the first "Rules of the Rue Morgue", maybe updating the scenario of the many end users currently exposed to the risk of failed failure analyses. Nevertheless, some constructive proposals will be also pointed out, as those exposed by a recent paper (Cassanelli et al., 2005) that, dealing with the challenges in system reliability...
In this paper, we demonstrate a practical alternative to the conventional SIL, which overcomes the above limitations. We show that it is possible to fabricate a lens directly on the back side of the silicon of the device under test. This lens works on principles of diffractive optics and is around 250 nm thick. The lens may be fabricated in about 1 hour, using a combination of FIB ion implantation...
This article presents a novel method to identify marginal faults in DRAM product via atomic force probing. Failing cells which are difficult to be identified by traditional methods were easily localized by current imaging. In addition, current-voltage curves were useful for judging failure root causes
Passive voltage contrast (PVC) using electron beam (E-beam) is the popular technique of the failure analysis procedure of real integrated circuit (IC) products. When the sample is exposed on the different energy electron beam, the surface of sample is charged positively or negatively. The charging characteristic is dependent on the secondary electron yield, but that is just qualitative analysis of...
The ITRS lists several areas where reliability technology needs development. This includes test methods for new materials and processes. However, perhaps the greatest change in reliability assurance is the requirement to place more of the responsibility for reliability assurance into the hands of circuit designers. This stems from the general compromising of reliability to obtain higher performance...
As IC manufacturing processes move to smaller feature sizes, fault isolation technique and debug become more and more challenging. In this paper, die level backside fault isolation case studies using emission microscope and scanning laser microscope are presented. They efficiently identified the fault sites in 0.13mum and 90nm products
This work illustrates succinctly the ability of the SCEM to provide valuable information for metrological studies of thick non-optically transparent semiconductor devices. The utility of SCEM to failure analysis comes from its ability to provide relatively high-resolution images from extremely thick specimens. In this way, the instrument can bridge the gap between optical SCOM useful for observing...
Scan/ATPG failures have been one of the main failures contributing to low yield issues and problems in microelectronics. In this paper, the beauty of the TetraMax diagnosis together with the Laker diagnosis software which serve as a complement was discussed, as they are one of the key diagnosis tools currently in the industry to analyze the scan/ATPG failures. The concept of the scan test, the files...
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