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This paper reports burn-in test results of Cu/low-K (BD) interconnects on flexible organic substrate (FR-4,0.1mm) and Si substrate. The electrical yields of via chains (via number: 11,182, via size: 0.26 to 0.5 mum) onto flexible organic substrate remain more than 50% and surviving via chains exhibit average resistance shift of 7.3% which is comparable to Si substrate (6.8%) after 524hrs (388hrs/75degC...
Increased packing density and reduced device size leads to increase in the back-end related delays. This happens as a result of increase in the metal resistance due to decreased line-width and increased capacitance due to a higher density of the interconnects. To minimize the impact of interconnect related delays (RC delay) the semiconductor industry had to, as a first order change, look for metal...
Electromigration and stress migration lifetimes are characterized as a function of metal thickness for Cu interconnects fabricated using 0.13 mum process technology. The stress migration lifetime decreases as metal thickness decreases, consistent with previous studies. The electromigration lifetime shows a more complicated dependence on metal thickness. For vias landing on narrow lines, the electromigration...
We presented a simulation concept which connects microstructural mechanical properties of copper films to the overall stress distribution. The underlying model is designed by combining several earlier models which describe different microstructural contributions to stress build up. The mechanical effects of surrounding layers are also included in our analysis. The analysis of the models and simulation...
Three novel CSP pad designs in a 0.18mum CMOS image sensor Cu interconnect technology were analyzed for use with a wafer level CSP (WLCSP) package. The CSP pad designs used various combinations of available aluminum and tungsten interconnect levels in order to improve the cross-sectional area without increasing the total stack height of the Cu interconnect technology. It was found that by increasing...
During the development and qualification of a 300mm low-k/Cu back end of line (BEOL) technology, the long-term reliability of such interconnects including low-k time-dependent dielectric breakdown (TDDB), Cu electromigration (EM), Cu stress migration (SM), and Cu/low-k thermal behavior are rapidly becoming one of the most critical challenges. In this paper, a comprehensive reliability evaluation for...
Nowadays, there are numbers of pad finishing types in market for ball grid array package (BGA). OSP (organic solderability preservatives) pad finishing technology is one of the most widely used for the purpose of increasing the joint strength and achieving more excellence in heat-resistance. Especially, to develop the ICs products to have compatibility with non-clean soldering fluxes and solder paste...
In this paper, inter layer dielectric characteristic ramped voltage breakdown (VBD) performance of multiplayer Cu/SiOC interconnect was studied. The results showed that the breakdown reliability is highly process-related. Some dominating factors, such as via etching process, integration scheme used and Cu/dielectric interface etc., were discussed and proposed to improve breakdown reliability performance
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