Technology shrinking and increasing design frequencies causes problems like IR drop. There are different types of IR drop issues like “Package-ball to bond-pad drop”, “bond-pad to internal global power ring drop” and “internal local power ring drops”. Optimization equations are developed to minimize trace wire length on package for P/G pads drawing highest current. The cost functions in the optimization target minimized IR drop for the regions of the chip that are switching at maximum speed. By use of our optimizing P/G pad placement, results on the USB TC chip shows an improvement about 28% to 33% in worst IR drop value for different types of power planning strategy.