We fabricate n-channel silicon bulk FinFET with silicon nitride (Si3N4) high- $ {\kappa } {\kappa } $ , and silicon dioxide (SiO2) low- $ {\kappa } $ spacers, and compare their performance using measurements and TCAD simulations. While all the three devices show similar dc performance, the ac and transient performance of low- $\kappa $ spacer FinFET is better due to lower parasitic capacitance ( ${C}_{\mathrm {par}}$ ). We show that ${C} _{\mathrm {par}}$ in SiO2 spacer FinFET is about half of that with Si3N4 spacer. When the gate length is scaled, the contribution of ${C} _{\mathrm {par}}$ compared with the intrinsic capacitance ( ${C} _{\mathrm {ox}}$ ) increases. For FinFET with Si3N4 spacers, ${C} _{\mathrm {par}}/{C} _{\mathrm {ox}}$ increases from 36% at 30-nm gate length to 105% when the gate length is scaled to 10 nm, while for FinFET with SiO2 spacers, the ratio changes from 19% to 55% making the latter more suitable for scaling. For SiO2 spacer FinFET, inverter delay is about 13% and 25% lower than Si3N4 spacer FinFET for gate lengths of 30 and 10 nm, respectively.