Hybrid scrambling technique is proposed for NROM-based ROMs in order to enhance the fabrication yield and reliability. Besides the traditional hardware redundancy techniques, fault masking features are also exploited to further improve the fabrication yield and reduce the amount of extra spare rows/columns. The hybrid scrambling technique basically consists of the row scrambling and the column scrambling techniques. Therefore, instead of scrambling a memory row/column, a logical memory cell can be scrambled into any of the logical memory cell address. This greatly improves the flexibility of scrambling. A hybrid scrambling control word is used for the control of the scrambling. Since the codes to be programmed into the NROM chips are known before programming, selecting a suitable code for programming a faulty NROM chip is helpful to further mask the faulty effects. Based on the proposed technique, possibilities of fault masking can be maximized. The proposed test and repair techniques can be easily incorporated into the ROM BIST architectures. According to experimental results, the fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.
Financed by the National Centre for Research and Development under grant No. SP/I/1/77065/10 by the strategic scientific research and experimental development program:
SYNAT - “Interdisciplinary System for Interactive Scientific and Scientific-Technical Information”.