In this brief, we have developed a charge-based model for the symmetric double-gate junctionless (JL) field effect transistor (FET) that also accounts for the inversion layer when the gate voltage is biased in deep depletion. Basically, this approach represents a generalization of a former model and aims at giving a unified description of JL FETs beyond the domain of operation for which they have been designed. In addition, to its interest for providing technology design rules, the new model is able to explain the unexpected increase in the gate capacitance when biasing the device in deep depletion as well as the theoretical limit for the OFF-current in deep depletion.
Financed by the National Centre for Research and Development under grant No. SP/I/1/77065/10 by the strategic scientific research and experimental development program:
SYNAT - “Interdisciplinary System for Interactive Scientific and Scientific-Technical Information”.