A compensated charge pump for use in phase-locked loops (PLLs) is presented, which reaches several of the desired design goals for this type of circuit. The measured mismatch between the source and sink currents is below 2.1% for a large output voltage headroom of 83.3% of the supply, while still having a high output resistance of 140 k??. This behaviour is reached with a novel dual compensation method. The circuit was implemented in a 180 nm CMOS technology using a 3 V supply.