This paper describes the investigation of a Plasma-Induced Damage (PID) event in the metal stack of an 8-in 130-nm-high volume process line. The relevant PID stress and measurement sequence used during standard productive fast Wafer Level Reliability Monitoring, which had detected this event, is discussed, and it is shown to be very effective. Additionally, hot carrier stress was performed on MOS transistors with antenna structures connected to the gate electrode for the quantification of the effect of PID on MOS device characteristics. It is demonstrated that the complete investigation can be done on production wafers in a very short time and only on scribe line test structures, saving time and hardware cost for extra wafers.
Financed by the National Centre for Research and Development under grant No. SP/I/1/77065/10 by the strategic scientific research and experimental development program:
SYNAT - “Interdisciplinary System for Interactive Scientific and Scientific-Technical Information”.