Nowadays, FPGA architecture has been improved rapidly, and more and more hard structures are integrated on heterogeneous FPGA chips. RTL technology mapping is one of methods to solve the problem of making use of those hard structures efficiently. However, the traditional RTL mapping tools can not do optimization on the delay on interconnect wires which can not be ignored in the current integrated circuit technology. So this paper focuses on an area and delay trade-off optimization, refers to improved inferring by more complex rules, and make use of simulated annealing algorithm to get a global optimization. The experiment results show our algorithm can give a 10% better optimization on delay.
