Incorporation of rare earth capping layers in the gate stack is an effective technique to tune the threshold V TH voltage of advance CMOS technologies. Furthermore, a reduction of the positive V TH drift (instability) has been reported for rare-earth doped nFETs under positive gate bias stress at high temperature. However, a non-optimized process can lead to an anomalous V TH behavior. We demonstrate that two independent components are responsible for this anomalous behavior which can be decoupled, individually studied, and then projected for meaningful lifetime extrapolations.