It is necessary that the condition of the steam turbines is continuously monitored on a scheduled basis for the safe operation of the steam turbines. The review showed that steam turbine fault detection and operation maintenance system (STFDOMS) is gaining importance recently. In this paper, novel hardware architecture is proposed for STFDOMS that can be communicated through the GSM network. Arduino is interfaced with the FPGA so as to transfer the message. The design has been simulated using the Verilog programming language and implemented in hardware using FPGA. The proposed system is shown to be a simple, cost effective and flexible and thereby making it suitable for the maintenance of steam turbines. This system forewarns the experts to access to data messages and take necessary action in a short period with great accuracy. The hardware developed is promised as a real-time test bench, specifically for investigations of long haul effects with different parameter settings.
Financed by the National Centre for Research and Development under grant No. SP/I/1/77065/10 by the strategic scientific research and experimental development program:
SYNAT - “Interdisciplinary System for Interactive Scientific and Scientific-Technical Information”.