SURVEY OF NETWORK ON CHIP ARCHITECTURES

Muhammad Athar Javed Sethi; Fawnizu Azmadi Hussin; Nor Hisham Hamid

SURVEY OF NETWORK ON CHIP ARCHITECTURES

Muhammad Athar Javed Sethi, Fawnizu Azmadi Hussin, Nor Hisham Hamid

Source

Sci.Int.(Lahore) > 2015 > 27 > 5 > 4133-4144

Abstract

Network on Chip (NoC) is a communication paradigm for on-chip communication. It has replaced the traditional bus and crossbar interconnection as it has higher bandwidth, modularity, scalability and benefits of resource reuse. This paper presents the detail survey of the NoC architectures being proposed and implemented in last more than a decade. Apart from comparing the NoC architectures on different parameters, detail information is also provided about these parameters of NoC architecture.

Authors

Muhammad Athar Javed Sethi

Fawnizu Azmadi Hussin

Nor Hisham Hamid

Resource added by

Muhammad Athar Javed Sethi

Keywords

Network on Chip (NoC) Routing algorithms Switching techniques Clocking mechanism

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Publication languages: English

Data set: Infona

Fields of science

Electrical Engineering, Electronic engineering, Information engineering

Bibliography

Jantsch, Axel; Kumar, Shashi; Millberg, Mikael; Oberg, Johny; Tiensyrja, Kari; Hemani, Ahmed; VLSI; Proceedings "A network on chip architecture and design methodology," in
Towles, Brian; William, J Dally "Route packets, not wires: on-chip interconnection networks,"
Greiner, Alain; Guerrier, Pierre "A generic architecture for on-chip packet-switched interconnections,"

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Muhammad Athar Javed Sethi

Fawnizu Azmadi Hussin

Nor Hisham Hamid

Resource added by

Muhammad Athar Javed Sethi

Keywords

Additional information

Fields of science

Report incorrect fields of science

Bibliography

Jantsch, Axel; Kumar, Shashi; Millberg, Mikael; Oberg, Johny; Tiensyrja, Kari; Hemani, Ahmed; VLSI; Proceedings "A network on chip architecture and design methodology," in

Towles, Brian; William, J Dally "Route packets, not wires: on-chip interconnection networks,"

Greiner, Alain; Guerrier, Pierre "A generic architecture for on-chip packet-switched interconnections,"

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SURVEY OF NETWORK ON CHIP ARCHITECTURES