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RF-CMOS process employing 14nm FinFET technology is introduced for the first time and its RF performance is characterized. Compared with its 28nm planar counterpart, the optimized 14nm RF FinFET consumes 63% of DC power with 53% of device active area and 3.8 times higher intrinsic gain (gm/gds). Based on the 14 nm technology, VNCAP with higher cap density (8%) and Q-factor (23%) is also verified for...
We review the operation mechanisms of the Z2-FET underlining its attractiveness as a capacitorless DRAM memory. The main parameters that govern the memory performance are discussed based on systematic experiments and simulations.
We demonstrate experimentally a capacitorless IT-DRAM fabricated with 28 nm FDSOI. The Z2-FET memory cell features a large current sense margin and long retention time at T = 25°C and 85°C. Systematic measurements show that Z2-FET exhibits negligible OFF-state current at low drain/gate bias and is suitable as a low-power embedded memory.
Electron tunneling is receiving increased emphasis as the physical mechanism of operation in emerging devices that seek to mitigate power dissipation issues in aggressively scaled CMOS technology. A tunneling field-effect transistors (TFET) consisting of a gated p-i-n junction is arguably the best known example. In a separate class of tunneling devices, consisting of two semiconducting layers separated...
Graphene and its derivatives (graphite, CNT) have very high conductivity and critical current density higher than 108 A/cm2, which can be utilized in interconnect applications. Theoretically, a doped graphene is predicted to have better performance than Cu as an interconnect conductor. However, the feasibility of graphene interconnect has not been experimentally examined systematically. In this paper,...
We will demonstrate a new digital driving technique for AMOLED using DeltaSigma modulation, which mitigates the TFT VT-shift issue with a simple 2-TFT-1-Cap pixel structure. It also solves the false image contour problem while achieving the same or better resolution and relaxed gate scan time compared with PWM. The system is implemented using a 2.2-inch QVGA AMOLED panel and FPGA.
We report on the fabrication of ZnO-based dual gate (DG) thin-film transistors (TFTs) with 20-nm-thick Al2O3 for both top and bottom dielectrics, which were deposited by atomic layer deposition on glass substrates at 200 degC. As characterized with single gate (SG), DG, and ground plane (GP) modes, our ZnO TFTs are well operated under 5 V. DG-mode TFT showed a field mobility of 0.38 cm2/V middots,...
Characterisation of a BioFET for detection of albumin in a mixture of human urine is presented. To avoid electrolyte effect of the urine, it was measured in PBS (phosphate buffer saline) at a fixed pH after albumin binding. The drain current was modulated by the albumin bound to the anti-albumin immobilised on the gate surface of the BioFET. The current variation ratio was likely to be proportional...
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