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A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F2. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation...
The increasing difficulties for further scaling down of Si CMOS is bringing to the fore the investigation of alternative channel materials. Among these, III-V compound semiconductors are very attractive due to their outstanding electron transport properties. This paper briefly reviews the prospects and the challenges for a III-V CMOS technology with gate lengths in the 10 nm range.
We have experimentally extracted the virtual-source electron injection velocity, vx0, of various III-V HFETs at room temperature. This is the carrier velocity that matters for logic applications of these transistors. Sub-100 nm devices with ??n > 10,000 cm2/V-s exhibit vx0 in excess of 3 ?? 107 cm/s even at VDD = 0.5 V. This is over 2 times that of state-of-the-art Si devices at VDD > 1. We...
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