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The work addresses benefits and performance impacts resulted from CMOS gate height reduction. The experiment shows that capacitance arising between the CMOS source/drain contact and the gate electrode decreases about linearly as the gate height scales down. The result also shows that stress liner techniques continue providing strong performance enhancement for CMOS as the gate height scales from 100...
Integration of low-dielectric constant SiCOH dielectrics (k~3) adjacent to gate stacks is demonstrated using 65 nm technology. Substantial reductions in parasitic capacitances are achieved through reductions in the outer fringe component of the overlap capacitance and the capacitance between the gate stack and metal contacts. These results are consistent with modeling. Although this is demonstrated...
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