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This work presents the design of a read-out channel suitable for application to silicon pixel detectors for the next generation Free Electron Laser (FEL) experiments. The readout architecture, which has been carried out in a 65 nm CMOS technology, consists of a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaping stage and a low-power analog-to-digital...
The high luminosity asymmetric e+e− collider SuperB, recently approved by the Italian Government, is designed to deliver a luminosity greater than 1036cm−2s−1 with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with...
This work presents an extensive analysis of the analog properties, in particular in terms of noise performance, of MOSFET devices belonging to a 65 nm low power CMOS technology exposed to ionizing radiation. The behavior of the 1/f and white noise terms is studied as a function of the main device parameters before and after exposure to 10 keV X-rays and 60Co γ-rays. The results provide a valuable...
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