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We have observed net optical gain by current injections to ultra-thin Si embedded in a resonant optical cavity. The cavity consists of a dielectric waveguide fabricated by CMOS and MEMS process. The photoluminescence (PL) spectra show narrow resonances peaked at the designed wavelength, and the electroluminescence (EL) intensity increases super-linearly with currents. The comparisons with first principle...
Resistive random access memory consisting of NiO resistive memories and control transistors was fabricated with 0.18-mum CMOS technology. An initial forming voltage as low as 2 V was achieved with thin NiO film, and a reset current lower than 100 muA was realized by using the current limit of a selected cell transistor in the set process (1T-1R). The current level was determined by its gate voltage,...
In this paper, we fabricated 1T1R NiO-ReRAM test circuits based on 0.18 mum CMOS technology and observed notable suppression of Ireset by imposing current compliance Icomp using a cell transistor. Reducing the stray capacitance between Pt/NiO/Pt and the cell transistor used as a current limiter is crucial in this issue. This enabled the systematic measurement of Icomp dependence of lreset for Icomp...
A high-speed, small-area DRAM sense amplifier with a threshold-voltage (VT) mismatch compensation function is proposed. This sense amplifier features a unique hierarchy data-line architecture with a direct sensing scheme which uses only nMOS transistors in the array, and a simple VT mismatch compensation circuitry which uses a pair of nMOS switching transistors. The layout area of the sense amplifier...
The authors present two developments for DRAM voltage limiters: a precise internal-voltage generator composed of a PMOS threshold-voltage-difference generator and a tunable voltage-up converter with fuse trimming; and a stabilized driver composed of a feedback amplifier with compensation for a time-dependent load. These circuits provide a voltage not susceptible to the supply-voltage and substrate-voltage...
The authors introduce a diagonal active stacked capacitor cell with a highly packed storage node (DASH) for use in a 16-Mb DRAM (dynamic random access memory). This novel cell features a storage capacitor formed above a bit line and the diagonal active area, which provides a large storage capacitance, 35 fF/bit, in a cell size of 3.4 mu m/sup 2/. The average charge retention time measured using an...
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