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We consider a new generation of COTS software routers (SRs), able to effectively exploit multi-Core/CPU HW platforms. Our main objective is to evaluate and to model the impact of power saving mechanisms, generally included in today's COTS processors, on the SR networking performance and behavior. To this purpose, we separately characterized the roles of both HW and SW layers through a large set of...
The concept of "green" and energy-efficient networking has begun to spread over the past few years, gaining an increasing popularity and interest from service and network providers, as well as equipment manufacturers. In this contribution, we propose an analytical framework that can effectively be adopted to optimize power consumption of a network device with respect to its expected forwarding...
This work is aimed at defining the architecture of a new digital ASIC, namely slow control logic (SCL), which will be designed and fabricated in a commercial 130 nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics proposed for future high-energy physics experiments at the super-Large Hadron Collider...
We consider a new generation of COTS software routers (SRs), able to effectively exploit multi-core/CPU HW platforms. Our main objective is to analyze, to evaluate and to model the impact of power saving mechanisms, generally included in today's COTS processors, on the SR behavior and networking performance. To this purpose, we tried to understand and to separately characterize the roles of both HW...
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