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Hot carrier (HC) reliability of gate-all-around twin Si nanowire field effect transistor (GAA TSNWFET) is reported and discussed with respect to size and shape of nanowire channel, gate length, thickness and kind of gate dielectric in detail. Smaller nanowire channel size, shorter gate length and thinner gate oxide down to 2 nm thickness show worse hot carrier reliability. The worst VD for 10 years...
Strained silicon nanowire transistor with embedded SiGe (e-SG) source/drain is investigated for the first time on experiments. By compressive stress induced by e-SG, PMOS performance is improved by about 85%. <110>-oriented nanowire channel also contributes 80% PMOS performance improvement relative to <100> direction. By combination of uniaxial stress and <110> channel direction,...
This paper describes TSNWFET devices with embedded Si1-xGex source/drain regions and different nanowire orientations. Thick Si1-xGex embedded source/drain and lang110rang channel orientation is found effective to enhance p-channel TSNWFET performance, while cause degradation for n-channel one. Thin Si1-xGex and lang100rang channel orientation is the preferred combination for keeping n-TSNWFET performance...
For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold...
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