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This paper presents the fabrication of single level cell (SLC), multi-level cell (MLC), triple-level cell (TLC) and quadruple level cell (QLC) using quantum dot gate non-volatile memory (QDNVM). QDNVM can store multiple bits in its discrete quantum dots in the gate region which represents different states of the memory cell. The precise control of charge storage in the discrete quantum dots I the...
This paper presents the circuit model of 3-state quantum dot gate FETs and design of three bit analog to digital converter (ADC) and digital to analog (DAC) converter based on that model.
This paper presents observation of intermediate state in quantum dot gate InGaAs FETs. The crosssectional schematic of a InGaAs FET consisting of a thin II-VI (nearly lattice matched) tunnel insulator was shown. Two layers of GeOx-cladded Ge dots are assembled on a multi-layered ZnSe/ZnMgS/ZnSe gate insualtor region (grown using a photoassisted metalorganic chemical vapor deposition technique) between...
This paper presents simulation of three-state behavior recently reported in quantum dot gate field-effect transistor (FET) structures. The model self-consistently solves Schrodinger and Poisson equations with built-in transfer of carriers from the inversion channel to two layers of cladded SiOx-Si quantum dots (QDs) forming the gate, predicting the "intermediate state" in the transfer Id...
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