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This paper describes the integration of the 20V complementary drain-extended MOS (DECMOS) and fully isolated drain-extended NMOS (DENMOS) transistors into a high-volume 0.13mum CMOS technology with two additional masks. The 20V devices were optimized for Rsp-BVdss performance without compromising the advanced 1.5V CMOS performance in the 0.35mum pitch copper, low-K dielectric process flow. This cost-effective...
The competitive PC peripheral application market drives the goal to develop a compressed, low-cost BiCMOS power technology with state-of-the-art specific-on-resistance (R/sub sp/) at the 20 V node. The 20 V rated lateral power device is difficult to optimize because modern VLSI processes tend to physically limit surface BV to about 13-19 V in planar devices. Here the structure performance is advanced...
Oxides used in EEPROMs have severe limitations placed on leakage currents due to long data retention time requirements. During write/erase (W/E) cycling, traps, responsible for both decreased tunneling currents and increased stress-induced leakage currents (SILCs), are generated inside the tunnel oxides. The decreased tunneling currents impose endurance limitations. The increased SILCs are partially...
The thickness of a silicided, phosphorous doped, n+ polysilicon gate electrode was varied, 220nm versus 140nm, to determine its impact on device scaling and performance. CMOS devices with physical gate lengths down to 0.15μm were fabricated utilizing a twin well, double level metal, fully planarized CMOS process. Differences in spacer geometry formation which impacted device short channel behavior...
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