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Trace buffers play a crucial role in curbing the obstacle of limited observability of internal states for error localization during post-silicon stage. Given the constraint of area over-head, selecting appropriate signals which are to be stored in the trace buffers is of paramount importance for the overall success of this observability enhancement mechanism. This paper proposes a register-transfer...
The success of trace buffer based techniques in post-silicon validation largely relies on selection of trace signals. Previous works have mainly focused on improving the metric of state restoration ratio. This metric though good at measuring enhancement of internal states visibility, does not reflect the effectiveness of selected trace signals in localizing post-silicon errors. It leads to increase...
A chip of embedded SRAM having backup circuits using a 60-nm c-axis aligned crystalline oxide semiconductor (CAAC-OS) such as CAAC indium-gallium-zinc oxide (CAAC-IGZO) and Cortex-M0 core having flip-flops with CAAC-OS backup circuits is fabricated. The SRAM and M0 core can retain data using the backup circuits during power-off; thus, they can perform power gating (PG) with backup time of 100 ns and...
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