The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We report on the implementation of an interleaving TDC architecture based on Virtex-4 ISERDES blocks. Multiple ISERDES blocks are used for each input channel in a split-phase arrangement. The architecture has moderate resolution (312 ps in this implementation), it is not sensitive to PVT variations, requires only limited FPGA resources, and thus suitable for high channel counts.
We demonstrate the potential for 1.85 Mbit/s secure key rates over 101 km of fiber, >100 times faster than previously demonstrated, using the differential phase shift quantum key distribution protocol and superconducting nanowire single-photon detectors.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.