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In this work we have proposed a fault tolerant reconfigurable Network-on-Chip (NoC) architecture that can endure router faults with graceful degradation in network performance. The routers which form the main building block of the interconnect network, have been modified to support multi-core connections. In case of router faults, the modified routers help to recover the healthy cores connected with...
This paper proposes an energy-efficient Network-on-Chip (NoC) topology called ZMesh, which is targeted towards the class of Constant-Geometry (CG) algorithms as well as generic traffic patterns. A simple technique has been followed to map functions to cores. The communication and traffic patterns of the considered algorithm class have been considered in synthesizing the proposed topology. The topology...
Traditional Mesh based Networks-on-Chips, are inherently slow due to hop-by-hop packet forwarding. The addition of Express Channels has emerged as a viable solution to reduce packet latency. However, there is a lack of application mapping methods, which can take into account the nature of the Express Channels. In this paper a constructive heuristic based approach has been proposed for application...
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