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The conduction mechanism in Ti/Si3N4/p-Si memory stack is described. In order to analyze the conduction mechanism, we measured the I-V characteristics in voltage sweep mode and conducted I-V curve fitting. And the temperature dependence in Ti/Si3N4/p-Si stacked cell is also investigated because we cannot claim the conduction mechanism just based on the I-V curve fitting. From I-V curve fitting and...
In this study, the gate-all-around (GAA) poly-Si channel flash memories with charge trap layer (Si3N4) have been successfully fabricated. Electric characteristics of fabricated devices including threshold voltage shift with program/erase operation have been investigated. Gate configurations were structured differently according to each defined channel width. Results show that devices with gate-all-around...
Most of research groups have studied on Tunneling Field-Effect Transistors (TFETs) with assumption that there are no gate/source overlap and abrupt source/channel junction. In this work, we study the electrical characteristics of double-gated thin-body TFET with gate/source overlap and no abrupt source/channel junction. From transfer characteristics, hump phenomenon occurring with increasing gate...
We have investigated the non-radiative recombination of GaN-based light-emitting diodes (LEDs) using electroluminescence (EL) and cathdoluminescence (CL) techniques. Comparing between EL and CL measurements, we can map the defects causing non-radiative recombination centers. At first, same size mapping techniques of these two measurements show defect-assisted non-radiative recombination. And enlarged...
Since recent mobile electronic devices have started to adopt NAND flash memory as their main data storage device, the demand for low cost and high density NAND flash memory has been rapidly increasing. As a promising candidate, nanowire SONOS NAND flash memory array has been introduced and reported for highly scalable device structure. However, since it is hard to bias floating body of memory cells,...
Structures of SiO2/SiOx/SiO2 and SiO2/SiOx/SiO2/SiOx/SiO 2 have been prepared on Si wafers by ion beam sputtering deposition in ultrahigh vacuum (UHV) and subsequently annealed to form single-layer and doubly stacked Si nanocrystals (NCs). Using these two structures, nonvolatile Si-NC floating-gate nMOSFETs were fabricated at x=1.6 following 1.5-mum CMOS standard procedures. The Fowler-Nordheim tunneling...
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